FPGA開発日記

カテゴリ別記事インデックス https://msyksphinz.github.io/github_pages , English Version https://fpgadevdiary.hatenadiary.com/

RISC-V Vector 1.0 をサポートするオープンソースCPU Araを試す (1. ビルド方法の調査)

github.com

AraはCVA6に対してベクトルユニットを追加したもの。RVV1.0をサポートする。

git clone https://github.com/pulp-platform/ara.git
git submodule update --init --recursive
  1. ツールチェインのビルド。
# Build the LLVM toolchain
make toolchain-llvm

ビルド後のツールチェインは install/riscv-llvm に格納されるようだ。

  1. Spikeのビルド。
# Build Spike
make riscv-isa-sim

ビルド後のSpikeは、install/riscv-isa-simに格納されるようだ。

  1. Verilatorのビルド。
# Build Verilator
make verilator

ビルド後のVerilatorは、install/verilatorに格納されるようだ。

  1. RISC-V GCCのビルド

これは、riscv-testsのビルドに必要だった。

make toolchain-gcc

ビルド後のGCCは、install/riscv-gccに格納されるようだ。

Araのコンフィグレーション

Araは現在以下のコンフィグレーション(というかレーン数)をサポートしている。

https://github.com/pulp-platform/ara/tree/main/config

Ara currently has four configurations, which differ on the amount of lanes:

  • 2_lanes.mk
  • 4_lanes.mk
  • 8_lanes.mk
  • 16_lanes.mk We also provide a default.mk configuration, which links to the 4_lanes one.

4レーンというのは、64-bit x 4 = 256-bitという意味だろうか？だとすると、DLEN=256ということかな？

RISC-V Testsの実行

# riscv-testsのビルド
cd apps
make riscv_tests # テストパタンのビルドが行われる

RTLシミュレーションの実行

cd hardware
make verilate # Veritaltorの場合はこのように。Modelsimの場合はmake compileのようだ
make riscv_tests_simv # テスト実行

テストパタンは以下に格納されている。

https://github.com/pulp-platform/ara/tree/main/apps/riscv-tests/isa/rv64uv

build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vaadd,elf &> build/rv64uv-ara-vaadd.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vaaddu,elf &> build/rv64uv-ara-vaaddu.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vsadd,elf &> build/rv64uv-ara-vsadd.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vsaddu,elf &> build/rv64uv-ara-vsaddu.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vsmul,elf &> build/rv64uv-ara-vsmul.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vssra,elf &> build/rv64uv-ara-vssra.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vssrl,elf &> build/rv64uv-ara-vssrl.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vnclip,elf &> build/rv64uv-ara-vnclip.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vnclipu,elf &> build/rv64uv-ara-vnclipu.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vadd,elf &> build/rv64uv-ara-vadd.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vsub,elf &> build/rv64uv-ara-vsub.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vrsub,elf &> build/rv64uv-ara-vrsub.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vwaddu,elf &> build/rv64uv-ara-vwaddu.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vwsubu,elf &> build/rv64uv-ara-vwsubu.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vwadd,elf &> build/rv64uv-ara-vwadd.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vwsub,elf &> build/rv64uv-ara-vwsub.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vsext,elf &> build/rv64uv-ara-vsext.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vzext,elf &> build/rv64uv-ara-vzext.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vadc,elf &> build/rv64uv-ara-vadc.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vmadc,elf &> build/rv64uv-ara-vmadc.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vsbc,elf &> build/rv64uv-ara-vsbc.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vmsbc,elf &> build/rv64uv-ara-vmsbc.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vand,elf &> build/rv64uv-ara-vand.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vor,elf &> build/rv64uv-ara-vor.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vxor,elf &> build/rv64uv-ara-vxor.trace
build/verilator/Vara_tb_verilator  -l ram,/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vsll,elf &> build/rv64uv-ara-vsll.trace

例えば、VLE32.v命令のテストパタンは以下のようなログが生成されていた。

build/rv64uv-ara-vle32.trace

Program header number 0 in `/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vle32' low is 80000000
Program header number 0 in `/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vle32' high is 80002acd
Program header number 1 in `/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vle32' high is 80003b7f
Program header number 2 in `/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vle32' high is 8000407f
Program header number 3 in `/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vle32' high is 80005187
Program header number 4 in `/home/msyksphinz/work/riscv/ara_vector/ara/apps/bin/rv64uv-ara-vle32' is not of type PT_LOAD; ignoring.
Set `ram TOP.ara_tb_verilator.dut.i_ara_soc.i_dram 10 0x80000000 0x100000 write with offset: 0x0 write with size: 0x5188
Simulation of Ara
=================

Simulation running, end by pressing CTRL-c.
*****Running tests for vle32.v*****
Checking the results of the test case 1:
PASSED.
Checking the results of the test case 3:
PASSED.
Checking the results of the test case 4:
PASSED.
Checking the results of the test case 5:
PASSED.
Checking the results of the test case 6:
PASSED.
Checking the results of the test case 7:
PASSED.
Checking the results of the test case 8:
PASSED.
Checking the results of the test case 9:
PASSED.
Checking the results of the test case 10:
PASSED.
Checking the results of the test case 11:
PASSED.
Checking the results of the test case 12:
PASSED.
Checking the results of the test case 14:
PASSED.
Checking the results of the test case 16:
PASSED.
Checking the results of the test case 17:
PASSED.
Checking the results of the test case 18:
PASSED.
Checking the results of the test case 19:
PASSED.
PASSED: /home/msyksphinz/work/riscv/ara_vector/ara/apps/riscv-tests/isa/rv64uv/vle32.c!
[hw-cycles]:           0
[152548] -Info: ara_tb_verilator.sv:49: Assertion failed in TOP.ara_tb_verilator: Core Test *** SUCCESS *** (tohost = 0)
- /home/msyksphinz/work/riscv/ara_vector/ara/hardware/tb/ara_tb_verilator.sv:52: Verilog $finish
Received $finish() from Verilog, shutting down simulation.

Simulation statistics
=====================
Executed cycles:  129f2
Wallclock time:   19.031 s
Simulation speed: 4007.88 cycles/s (4.00788 kHz)

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