object SimdAddNaxGen extends App{
import naxriscv.compatibility._
import naxriscv.utilities._
def plugins = {
//Get a default list of pluginsval l = Config.plugins(
withRdTime = false,
aluCount = 2,
decodeCount = 2
)
//Add our plugin to the two ALUs
l += new SimdAddPlugin("ALU0")
l += new SimdAddPlugin("ALU1")
l
}
//Create a SpinalHDL configuration that will be used to generate the hardwareval spinalConfig = SpinalConfig(inlineRom = true)
spinalConfig.addTransformationPhase(new MemReadDuringWriteHazardPhase)
spinalConfig.addTransformationPhase(new MultiPortWritesSymplifier)
//Generate the NaxRiscv verilog fileval report = spinalConfig.generateVerilog(new NaxRiscv(xlen = 32, plugins))
//Generate some C header files used by the verilator testbench to connect to the DUT
report.toplevel.framework.getService[DocPlugin].genC()
}
object SimdAddRawPlugin{
val SEL = Stageable(Bool()) //Will be used to identify when we are executing a ADD4val ADD4 = IntRegFile.TypeR(M"0000000----------000-----0001011")
}
class SimdAddRawPlugin(euId : String) extends Plugin {
import SimdAddRawPlugin._
val setup = create early new Area{
val eu = findService[ExecutionUnitBase](_.euId == euId)
eu.retain() //We don't want the EU to generate itself before we are done with it//Specify all the ADD4 requirements
eu.addMicroOp(ADD4)
eu.setCompletion(ADD4, stageId = 0)
eu.setStaticWake(ADD4, stageId = 0)
eu.setDecodingDefault(SEL, False)
eu.addDecoding(ADD4, SEL, True)
//IntFormatPlugin provide a shared point to write into the register file with some optional carry extensionsval intFormat = findService[IntFormatPlugin](_.euId == euId)
val writeback = intFormat.access(stageId = 0, writeLatency = 0)
}
val logic = create late new Area{
val eu = setup.eu
val writeback = setup.writeback
val stage = eu.getExecute(stageId = 0)
//Get the RISC-V RS1/RS2 values from the register fileval rs1 = stage(eu(IntRegFile, RS1)).asUInt
val rs2 = stage(eu(IntRegFile, RS2)).asUInt
//Do some computationval rd = UInt(32 bits)
rd( 7 downto 0) := rs1( 7 downto 0) + rs2( 7 downto 0)
rd(16 downto 8) := rs1(16 downto 8) + rs2(16 downto 8)
rd(23 downto 16) := rs1(23 downto 16) + rs2(23 downto 16)
rd(31 downto 24) := rs1(31 downto 24) + rs2(31 downto 24)
//Provide the computation value for the writeback
writeback.valid := stage(SEL)
writeback.payload := rd.asBits
//Now the EU has every requirements set for the generation (from this plugin perspective)
eu.release()
}
}
