Tenstorrentが、オープンソースのRISC-VベクトルプロセッサOcelotを公開した。
Oceletの環境にて、以前作成したmemcpyのコードを実行してみた。しかしなぜかエラーが出る。
copy_data_vec: mv a3, a0 # Copy destination .loop: vsetvli t0, a3, e8,m1 # Vectors of 8b vle8.v v0, (a1) # Load bytes add a1, a1, t0 # Bump pointer sub a2, a2, t0 # Decrement count vse8.v v0, (a3) # Store bytes add a3, a3, t0 # Bump pointer bnez a2, .loop # Any more? ret # Return
もしやと思って全部のテストコードを流してみた。やっぱりアサーションで落ちる。これは基本的なコンフィグレーションがうまく動いていないのでは？
make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-andi.out] Error 255 [7000] %Error: chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomVecConfig/chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-bne.out] Error 255 [7000] %Error: chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomVecConfig/chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-slti.out] Error 255 [7000] %Error: chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomVecConfig/chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-srai.out] Error 255 [8000] %Error: chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomVecConfig/chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-slli.out] Error 255 [7000] %Error: chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomVecConfig/chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-beq.out] Error 255 [7000] %Error: chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomVecConfig/chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-addi.out] Error 255 [8000] %Error: chipyard.TestHarness.MediumBoomVecConfig.top.v:411484: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor
MediumBoomVecConfig以外でも試してみたほうがよさそうだ。RocketConfigとMediumConfigで作ってみよう。
$ make CONFIG=MediumBoomConfig
MediumBoomConfigでもだめ。
make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomConfig/rv64ui-p-lbu.out] Error 255 [24000] %Error: chipyard.TestHarness.MediumBoomConfig.top.v:374485: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomConfig/chipyard.TestHarness.MediumBoomConfig.top.v:374485: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomConfig/rv64ui-p-lb.out] Error 255 [24000] %Error: chipyard.TestHarness.MediumBoomConfig.top.v:374485: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomConfig/chipyard.TestHarness.MediumBoomConfig.top.v:374485: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomConfig/rv64ui-p-lw.out] Error 255 [24000] %Error: chipyard.TestHarness.MediumBoomConfig.top.v:374485: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomConfig/chipyard.TestHarness.MediumBoomConfig.top.v:374485: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomConfig/rv64ui-p-lh.out] Error 255 [24000] %Error: chipyard.TestHarness.MediumBoomConfig.top.v:374485: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomConfig/chipyard.TestHarness.MediumBoomConfig.top.v:374485: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomConfig/rv64ui-p-lhu.out] Error 255 [26000] %Error: chipyard.TestHarness.MediumBoomConfig.top.v:374725: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.buffer_1.monitor %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomConfig/chipyard.TestHarness.MediumBoomConfig.top.v:374725: Verilog $stop Aborting... make: *** [/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/common.mk:256: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomConfig/rv64ui-p-sb.out] Error 255
$ make CONFIG=RocketConfig
RocketConfigならOKだ。BOOMの何かが壊れている？
[ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-jal.out Completed after 130229 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-jalr.out Completed after 130359 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-lb.out Completed after 162306 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-lbu.out Completed after 161930 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-lh.out Completed after 161690 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-lhu.out Completed after 161199 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-lui.out Completed after 130240 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-lw.out Completed after 162285 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-or.out Completed after 161743 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-ori.out Completed after 130598 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sb.out Completed after 179195 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sh.out Completed after 180116 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sw.out Completed after 178449 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sll.out Completed after 161702 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-slli.out Completed after 148295 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-slt.out Completed after 149050 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-slti.out Completed after 130733 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sra.out Completed after 161647 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-srai.out Completed after 130739 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-srl.out Completed after 161967 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-srli.out Completed after 148298 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sub.out Completed after 148792 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-xor.out Completed after 162092 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-xori.out Completed after 130593 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-addw.out Completed after 148825 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-addiw.out Completed after 130707 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-ld.out Completed after 178937 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-lwu.out Completed after 161247 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sd.out Completed after 193188 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-slliw.out Completed after 148325 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sllw.out Completed after 161734 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sltiu.out Completed after 130733 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sltu.out Completed after 161569 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sraiw.out Completed after 148398 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-sraw.out Completed after 161964 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-srliw.out Completed after 148349 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.RocketConfig/rv64ui-v-srlw.out Completed after 162426 cycles
