なんとなくチェックするとTenstorrentのRISC-V VectorコアOcelotのリビジョンがまた上がっていた。
多少はテストベンチが通るようになっただろうか?
- Chipyardのリビジョン:
2a9a844e1fbf4958cf10f69810a8febac065c100
- Boomのリビジョン:
a2cdc47b3bb52f4e433fdc3b4a0fd89e0233ec36
Condaによる環境を整えるためには、./build-setup.sh
を少し改造してFireSim/FireMartialをインストールしないようにした。
# # setup firesim # if run_step "6"; then # $CYDIR/scripts/firesim-setup.sh # $CYDIR/sims/firesim/gen-tags.sh # # # precompile firesim scala sources # if run_step "7"; then # pushd $CYDIR/sims/firesim # ( # echo $CYDIR # source sourceme-f1-manager.sh --skip-ssh-setup # pushd sim # make sbt SBT_COMMAND="project {file:$CYDIR}firechip; compile" TARGET_PROJECT=firesim # popd # ) # popd # fi # fi # # # setup firemarshal # if run_step "8"; then # pushd $CYDIR/software/firemarshal # ./init-submodules.sh # # # precompile firemarshal buildroot sources # if run_step "9"; then # source $CYDIR/scripts/fix-open-files.sh # ./marshal $VERBOSE_FLAG build br-base.json # ./marshal $VERBOSE_FLAG clean br-base.json # fi # popd # fi
最後までセットアップが走ることができるので、env.sh
にきちんとした情報が残ることができる。
# line auto-generated by init-submodules-no-riscv-tools.sh __DIR="$(dirname "$(readlink -f "${BASH_SOURCE[0]:-${(%):-%x}}")")" PATH=$__DIR/bin:$PATH PATH=$__DIR/software/firemarshal:$PATH # line auto-generated by build-toolchains.sh source /home/kimura/work/riscv/chipyard/chipyard-ocelot/env-riscv-tools.sh # line auto-generated by init-submodules-no-riscv-tools.sh __DIR="/home/kimura/work/riscv/chipyard/chipyard-ocelot" PATH=$__DIR/software/firemarshal:$PATH # line auto-generated by init-submodules-no-riscv-tools.sh __DIR="/home/kimura/work/riscv/chipyard/chipyard-ocelot" PATH=$__DIR/software/firemarshal:$PATH # line auto-generated by init-submodules-no-riscv-tools.sh __DIR="/home/kimura/work/riscv/chipyard/chipyard-ocelot" PATH=$__DIR/software/firemarshal:$PATH # line auto-generated by init-submodules-no-riscv-tools.sh __DIR="/home/kimura/work/riscv/chipyard/chipyard-ocelot" PATH=$__DIR/software/firemarshal:$PATH # line auto-generated by init-submodules-no-riscv-tools.sh __DIR="/home/kimura/work/riscv/chipyard/chipyard-ocelot" PATH=$__DIR/software/firemarshal:$PATH # line auto-generated by init-submodules-no-riscv-tools.sh __DIR="/home/kimura/work/riscv/chipyard/chipyard-ocelot" PATH=$__DIR/software/firemarshal:$PATH # line auto-generated by init-submodules-no-riscv-tools.sh __DIR="/home/kimura/work/riscv/chipyard/chipyard-ocelot" PATH=$__DIR/software/firemarshal:$PATH # line auto-generated by ./build-setup.sh conda activate /home/kimura/work/riscv/chipyard/chipyard-ocelot/.conda-env source /home/kimura/work/riscv/chipyard/chipyard-ocelot/scripts/fix-open-files.sh
次に、Verilatorの環境を構築するために、sims/verilator/Makefile
を修正する。
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index a76ce264..24a62ba5 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -169,6 +169,7 @@ VERILATOR_NONCC_OPTS = \ $(PREPROC_DEFINES) \ --top-module $(VLOG_MODEL) \ --vpi \ + +incdir+$(GEN_COLLATERAL_DIR)/ \ -f $(sim_common_files)
これでSmallVecConfig
がビルドできるようになった。
make CONFIG=SmallBoomVecConfig
make CONFIG=SmallBoomVecConfig run-asm-tests
テストはちゃんと流れるようになったな。
mkdir -p /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig ln -fs /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/.conda-env/riscv-tools/riscv64-unknown-elf/share/riscv-tests/isa/rv64ud-v-ldst /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-ldst (set -o pipefail && /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/simulator-chipyard-SmallBoomVecConfig +permissive +dramsim +dramsim_ini_dir=/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +verbose +permissive-off /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-ldst </dev/null 2> >(spike-dasm > /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-ldst.out) | tee /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-ldst.log) [UART] UART0 is here (stdin/stdout). mkdir -p /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig ln -fs /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/.conda-env/riscv-tools/riscv64-unknown-elf/share/riscv-tests/isa/rv64ud-v-move /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-move (set -o pipefail && /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/simulator-chipyard-SmallBoomVecConfig +permissive +dramsim +dramsim_ini_dir=/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +verbose +permissive-off /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-move </dev/null 2> >(spike-dasm > /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-move.out) | tee /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-move.log) [UART] UART0 is here (stdin/stdout). mkdir -p /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig ln -fs /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/.conda-env/riscv-tools/riscv64-unknown-elf/share/riscv-tests/isa/rv64ud-v-fcmp /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-fcmp (set -o pipefail && /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/simulator-chipyard-SmallBoomVecConfig +permissive +dramsim +dramsim_ini_dir=/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +verbose +permissive-off /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-fcmp </dev/null 2> >(spike-dasm > /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-fcmp.out) | tee /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.SmallBoomVecConfig/rv64ud-v-fcmp.log) [UART] UART0 is here (stdin/stdout).
ベクトルのテストベンチを流してみよう。
./simulator-chipyard-SmallBoomVecConfig +permissive +dramsim +dramsim_ini_dir=/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +verbose +permissive-off /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/tests/rvv/kernels/inner_product/inner-prod-unroll-vector.elf
3 0x0000000080002500 (0x00000517) x10 0x0000000080002500 3 0x0000000080002504 (0x6c850513) x10 0x0000000080002bc8 3 0x0000000080002508 (0x00001597) x11 0x0000000080003508 3 0x000000008000250c (0x6c058593) x11 0x0000000080003bc8 3 0x0000000080002510 (0x40000613) x12 0x0000000000000400 3 0x0000000080002514 (0x0d1676d7) x13 0x0000000000000010 3 0x0000000080002518 (0x0221b257) 3 0x000000008000251c (0x0223b357) [102000] %Error: BoomCore.sv:1973: Assertion failed in TOP.TestHarness.chiptop.system.tile_prci_domain.tile_reset_domain_boom_tile.core: Assertion failed: Pipeline has hung. at core.scala:1480 assert (!(idle_cycles.value(13)), "Pipeline has hung.") %Error: /home/kimura/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.SmallBoomVecConfig/gen-collateral/BoomCore.sv:1973: Verilog $stop Aborting...
あれれ、ハングしてしまった...