久しぶりにTenstorrentのOcelotの最新版を試行してみることにした。 OcelotはBOOMをベースとした、RISC-V Vectorの実装で、Tenstorrentがオープンソースとして公開している。
一応テストケースはPASSできるみたいだ。動作確認をした。
[ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-simple.out Completed after 4151 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-add.out Completed after 10722 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-addi.out Completed after 7731 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-and.out Completed after 11224 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-andi.out Completed after 6732 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-auipc.out Completed after 4432 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-beq.out Completed after 7957 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-bge.out Completed after 8552 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-bgeu.out Completed after 9484 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-p-blt.out Completed after 7957 cycles ... [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-v-slliw.out Completed after 145612 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-v-sllw.out Completed after 156988 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-v-sltiu.out Completed after 128002 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-v-sltu.out Completed after 156222 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-v-sraiw.out Completed after 145646 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-v-sraw.out Completed after 157138 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-v-srliw.out Completed after 145778 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-v-srlw.out Completed after 157118 cycles [ PASSED ] /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/output/chipyard.TestHarness.MediumBoomVecConfig/rv64ui-v-subw.out Completed after 146388 cycles
しかし、肝心のベクトルのテストケースがPASSしない。デバッグモードにして命令をトレースして実行してみた。
diff --git a/src/main/scala/common/config-mixins.scala b/src/main/scala/common/config-mixins.scala index f4639bc5..08075db6 100644 --- a/src/main/scala/common/config-mixins.scala +++ b/src/main/scala/common/config-mixins.scala @@ -92,6 +92,7 @@ class WithRationalBoomTiles extends Config((site, here, up) => { class WithVector(coreWidth: Int = 1) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( + enableCommitLogPrintf = true, enableVector = true, enableFastLoadUse = false, // Vector Unit doesn't support replay setvLen = 256,
./simulator-chipyard-MediumBoomVecConfig +verbose +permissive +dramsim +dramsim_ini_dir=/home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +verbose +permissive-off /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/tests/rvv/kernels/axpy/axpy-vector.elf 2>&1 | sed 's/(0x/DASM(0x/g' | ${HOME}/riscv64/bin/spike-dasm
3 0x0000000080001b5c fsd fa5, 0(a5) 3 0x0000000080001b60 addi a5, a5, 8 x15 0x0000000080b1dfc0 3 0x0000000080001b64 bne a5, a7, pc - 8 3 0x0000000080001b68 auipc a5, 0x0 x15 0x0000000080001b68 3 0x0000000080001b6c fld fa0, 232(a5) f10 0x3ff0000000000000 3 0x0000000080001b70 auipc ra, 0x0 x 1 0x0000000080001b70 3 0x0000000080001b74 jalr ra, ra, -704 x 1 0x0000000080001b78 3 0x00000000800018b0 vsetvli a5, a2, e64, m8, ta, mu x15 0x0000000000000020 3 0x00000000800018b4 vfmv.v.f v16, fa0 3 0x00000000800018b8 bge zero, a2, pc + 80 3 0x00000000800018bc vle64.v v8, (a0) 3 0x00000000800018c0 vle64.v v24, (a1) 3 0x00000000800018c4 sext.w a4, a5 x14 0x0000000000000020 3 0x00000000800018c8 vsetvli zero, zero, e64, m8, tu, mu 3 0x00000000800018cc vfmacc.vv v24, v8, v16 - Verilated::debug attempted, but compiled without VL_DEBUG, so messages suppressed. - Suggest remake using 'make ... CPPFLAGS=-DVL_DEBUG' %Error: /home/msyksphinz/work/riscv/chipyard/chipyard-ocelot/sims/verilator/generated-src/chipyard.TestHarness.MediumBoomVecConfig/chipyard.TestHarness.MediumBoomVecConfig.harness.v:28715: Verilated model didn't converge - See https://verilator.org/warn/DIDNOTCONVERGE Aborting...
うーむ、VLE命令は動作していそうだが、VFMACCで失敗した。Verilator向けに改造した部分が良くなかったかな。引き続き調査する。
