riscv-arch-testは、riscv-testsとは別に管理されているRISC-Vのテストスイートである。
これまでちゃんと使ったことが無かったので、ここら辺で少し触ってみておこうと思う。 まずはSpikeでの動作確認から。
リポジトリをクローンする。
git clone https://github.com/riscv-non-isa/riscv-arch-test.git
つぎに別のディレクトリにSpikeをクローンしておく。
git clone https://github.com/riscv-software-src/riscv-isa-sim.git
riscv-arch-testの中でターゲットをSpikeに設定し、XLEN=64とする。このためには、riscv-isa-sim/arch_test_targetからMakefile.inをコピーしてriscv-arch-testの直下にコピーする。
その後、以下のように書き換えを行った。
diff --git a/Makefile.include b/Makefile.include index bb81e0d..d2bfc04 100644 --- a/Makefile.include +++ b/Makefile.include @@ -1,23 +1,16 @@ # set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target -export TARGETDIR ?= $(ROOTDIR)/riscv-target +export TARGETDIR ?= /home/msyksphinz/work/riscv/msrh/riscv-isa-sim/arch_test_target # set XLEN to max supported XLEN. Allowed values are 32 and 64 -export XLEN ?= 32 +export XLEN ?= 64 # name of the target. Note a folder of the same name must exist in the TARGETDIR directory export RISCV_TARGET ?= spike
これでmake compileを実行すると、まずはSpike用のバイナリが作成される。
============================ VARIABLE INFO ==================================
ROOTDIR: /home/msyksphinz/work/riscv/msrh/riscv-arch-test [origin: file]
WORK: /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work [origin: file]
TARGETDIR: /home/msyksphinz/work/riscv/msrh/riscv-isa-sim/arch_test_target [origin: file]
RISCV_TARGET: spike [origin: file]
XLEN: 64 [origin: file]
RISCV_DEVICE: I [origin: file]
=============================================================================
make -j1 \
RISCV_TARGET=spike \
RISCV_DEVICE=I \
compile -C /home/msyksphinz/work/riscv/msrh/riscv-arch-test/riscv-test-suite/rv64i_m/I
make[1]: Entering directory '/home/msyksphinz/work/riscv/msrh/riscv-arch-test/riscv-test-suite/rv64i_m/I'
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/add-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/addi-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/addiw-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/addw-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/and-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/andi-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/auipc-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/beq-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/bge-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/bgeu-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/blt-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/bltu-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/bne-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/jal-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/jalr-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/lb-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/lbu-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/ld-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/lh-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/lhu-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/lui-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/lw-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/lwu-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/or-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/ori-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sb-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sd-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sh-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sll-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/slli-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/slliw-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sllw-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/slt-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/slti-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sltiu-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sltu-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sra-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/srai-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sraiw-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sraw-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/srl-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/srli-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/srliw-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/srlw-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sub-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/subw-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/sw-align-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/xor-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/xori-01.elf
Compile /home/msyksphinz/work/riscv/msrh/riscv-arch-test/work/rv64i_m/I/fence-01.elf
make[1]: Leaving directory '/home/msyksphinz/work/riscv/msrh/riscv-arch-test/riscv-test-suite/rv64i_m/I'
