DATE 2022
1.1 Scalable quantum stacks: current status and future prospects
- FULL-STACK QUANTUM COMPUTING SYSTEMS IN THE NISQ ERA: ALGORITHM-DRIVEN AND HARDWARE-AWARE COMPILATION TECHNIQUES
- TWEEDLEDUM: A COMPILER COMPANION FOR QUANTUM COMPUTING
- A CRYO-CMOS TRANSMON QUBIT CONTROLLER AND VERIFICATION WITH FPGA EMULATION
2.1 Energy-autonomous systems for next generation of IoT
- MICROPOWER MANAGEMENT TECHNIQUES FOR ENERGY HARVESTING APPLICATIONS
- FULLY SELF-POWERED WIRELESS SENSORS ENABLED BY OPTIMIZED POWER MANAGEMENT MODULES
- DESIGN OF SELF-SUSTAINING CONNECTED SMART DEVICES
5.1 Novel Design Techniques for Emerging Technologies in Computing
- Physically & Algorithmically secure logic locking with hybrid CMOS/NanoMagnet logic circuits
- Exploring standard-cell design for reconfigurable nanotechnologies: A formal approach
- Design enablement of CFET devices for sub-2nm CMOS nodes
- Majority-based design flow AQFP superconducting family
6.1 Alternative design paradigms for sustainable IoT nodes
- Bio-inspired energy efficient all-spiking internet of things nodes
- Hybrid digital-analog systems-on-chip for efficient edge AI
- 3D compute cubes for edge intelligence: Nanoelectric enabled adaptive systems based on junctionless ambipolar, and ferroelectric vertical FETs
11.1 Analog / mixed-signal EDA from system level to layout level
- EFFICSENSE: AN ARCHITECTURAL PATHFINDING FRAMEWORK FOR ENERGY-CONSTRAINED SENSOR APPLICATIONS
- TOPOLOGY OPTIMIZAITON OF OPERATIONAL AMPLIFIER IN CONTINUOUS SPACE VIA GRAPH EMBEDDING
- A CHARGE FLOW FORMULATION FOR GUIDING ANALOG/MIXED-SIGNAL PLACEMENT
- ARE ANALYTICAL TECHNIQUES WORTHWHILE FOR ANALOG IC PLACEMENT?
- ROUTABILITY-AWARE PLACEMENT FOR ADVANCED FINFET MIXED-SIGNAL CIRCUITS USING SATISFIABILITY MODULO THEORIES
- CONSTRUCTIVE COMMON-CENTROID PLACEMENT AND ROUTING FOR BINARY-WEIGHTED CAPACITOR ARRAYS
11.2 Approximate Computing Everywhere
- MUSCAT: MUS-BASED CIRCUIT APPROXIMATION TECHNIQUE
- OPACT: OPTIMIZATION OF APPROXIMATE COMPRESSOR TREE FOR APPROXIMATE MULTIPLIER
- LEARNING TO DESIGN ACCURATE DEEP LEARNING ACCELERATORS WITH INACCURATE MULTIPLIERS
- CROSS-LAYER APPROXIMATION FOR PRINTED MACHINE LEARNING CIRCUITS
- A TARGET-SEPARABLE BWN INSPIRED SPEECH RECOGNITION PROCESSOR WITH LOW-POWER PRECISION-ADAPTIVE APPROXIMATE COMPUTING
- TOWARDS ENERGY-EFFICIENT CGRAS VIA STOCHASTIC COMPUTING
11.3 Advanced Mapping and Optimization for Emerging ML Hardware
- DASC : A DRAM DATA MAPPING METHODOLOGY FOR SPARSE CONVOLUTIONAL NEURAL NETWORKS
- VW-SDK: EFFICIENT CONVOLUTIONAL WEIGHT MAPPING USING VARIABLE WINDOWS FOR PROCESSING-IN-MEMORY ARCHITECTURES
- A UNIFORM LATENCY MODEL FOR DNN ACCELERATORS WITH DIVERSE ARCHITECTURES AND DATAFLOWS
- MEDEA: A MULTI-OBJECTIVE EVOLUTIONARY APPROACH TO DNN HARDWARE MAPPING
- DIGAMMA: DOMAIN-AWARE GENETIC ALGORITHM FOR HW-MAPPING CO-OPTIMIZATION FOR DNN ACCELERATORS
- ANACONGA: ANALYTICAL HW-CNN CO-DESIGN USING NESTED GENETIC ALGORITHMS
11.4 Reconfigurable Systems
- ADAFLOW: A FRAMEWORK FOR ADAPTIVE DATAFLOW CNN ACCELERATION ON FPGAS
- RAW FILTERING OF JSON DATA ON FPGAS
- GRAPHWAVE: A HIGHLY-PARALLEL COMPUTE-AT-MEMORY GRAPH PROCESSING ACCELERATOR
- RF-CGRA: A ROUTING-FRIENDLY CGRA WITH HIERARCHICAL REGISTER CHAINS
- PATHSEEKER: A FAST MAPPING ALGORITHM FOR CGRAS
- IMPROVING TECHNOLOGY MAPPING FOR AIC-BASED FPGAS
11.5 An Industrial Perspective on Autonomous Systems Design
- SYMBIOTIC SAFETY: SAFE AND EFFICIENT HUMAN-MACHINE COLLABORATION BY UTILIZING RULES
- A MIDDLEWARE JOURNEY FROM MICROCONTROLLERS TO MICROPROCESSORS
- RELIABLE DISTRIBUTED SYSTEMS
- PAVE 360 - A PARADIGM SHIFT IN AUTONOMOUS DRIVING VERIFICATION WITH A DIGITAL TWIN
12.1 AI as a Driver for Innovative Applications
- ALGORITHM-HARDWARE CO-DESIGN FOR EFFICIENT BRAIN-INSPIRED HYPERDIMENSIONAL LEARNING ON EDGE
- POISONHD: POISON ATTACK ON BRAIN-INSPIRED HYPERDIMENSIONAL COMPUTING
- AIME: WATERMARKING AI MODELS BY LEVERAGING ERRORS
- THINGNET: A LIGHTWEIGHT REAL-TIME MIRAI IOT VARIANTS HUNTER THROUGH CPU POWER FINGERPRINTING
- M2M-ROUTING: ENVIRONMENTAL ADAPTIVE MULTI-AGENT REINFORCEMENT LEARNING BASED MULTI-HOP ROUTING POLICY FOR SELF-POWERED IOT SYSTEMS
12.2 Applications of optimized quantum and probabilistic circuits in emergent computing systems
- MUZZLE THE SHUTTLE: EFFICIENT COMPILATION FOR MULTI-TRAP TRAPPED-ION QUANTUM COMPUTERS
- CIRCUITS FOR MEASUREMENT BASED QUANTUM STATE PREPARATION
- OPTIC: A PRACTICAL QUANTUM BINARY CLASSIFIER FOR NEAR-TERM QUANTUM COMPUTERS
- SCALABLE VARIATIONAL QUANTUM CIRCUITS FOR AUTOENCODER-BASED DRUG DISCOVERY
- TOWARDS LOW-COST HIGH-ACCURACY STOCHASTIC COMPUTING ARCHITECTURE FOR UNIVARIATE FUNCTIONS: DESIGN AND DESIGN SPACE EXPLORATION
12.3 Reliable safe and approximate systems
- DO TEMPERATURE AND HUMIDITY EXPOSURES HURT OR BENEFIT YOUR SSDS?
- SAFEDM: A HARDWARE DIVERSITY MONITOR FOR REDUNDANT EXECUTION ON NON-LOCKSTEPPED CORES
- IS APPROXIMATION UNIVERSALLY DEFENSIVE AGAINST ADVERSARIAL ATTACKS IN DEEP NEURAL NETWORKS?
- RELIABILITY ANALYSIS OF A SPIKING NEURAL NETWORK HARDWARE ACCELERATOR
- RELIABILITY OF GOOGLE’S TENSOR PROCESSING UNITS FOR EMBEDDED APPLICATIONS
12.4 Raising Performance and Reliability of the Memory Subsystem
- STEALTH ECC: A DATA-WIDTH AWARE ADAPTIVE ECC SCHEME FOR DRAM ERROR RESILIENCE
- ACCELERATE HARDWARE LOGGING TO EFFICIENTLY GUARANTEE PM CRASH CONSISTENCY
- MEMPOOL-3D: BOOSTING PERFORMANCE AND EFFICIENCY OF SHARED-L1 MEMORY MANY-CORE CLUSTERS WITH 3D INTEGRATION
- REPAIR: A RERAM-BASED PROCESSING-IN-MEMORY ACCELERATOR FOR INDEL REALIGNMENT
- SIC PROCESSORS FOR EXTREME HIGH-TEMPERATURE VENUS SURFACE EXPLORATION
12.5 Bringing Robust Deep Learning to the Autonomous Edge: New Challenges and Algorithm-Hardware Solutions
- UNSUPERVISED TEST-TIME ADAPTATION OF DEEP NEURAL NETWORKS AT THE EDGE: A CASE STUDY
- SUPER-EFFICIENT SUPER RESOLUTION FOR FAST ADVERSARIAL DEFENSE AT THE EDGE
- FAULT-TOLERANT DEEP NEURAL NETWORKS FOR PROCESSING-IN-MEMORY BASED AUTONOMOUS EDGE SYSTEMS
- FRL-FI: TRANSIENT FAULT ANALYSIS FOR FEDERATED REINFORCEMENT LEARNING-BASED NAVIGATION SYSTEMS
13.1 New Perspectives in Test and Diagnosis
- IMPROVING CELL-AWARE TEST FOR INTRA-CELL SHORT DEFECTS
- APUF FAULTS: IMPACT, TESTING, AND DIAGNOSIS
- GRAPH NEURAL NETWORK-BASED DELAY-FAULT LOCALIZATION FOR MONOLITHIC 3D ICS
- A COMPACTION METHOD FOR STLS FOR GPU IN-FIELD TEST
13.2 From system-level specification to RTL and back
- AUTOMATIC GENERATION OF ARCHITECTURE-LEVEL MODELS FROM RTL DESIGNS FOR PROCESSORS AND ACCELERATORS
- TWINE: A CHISEL EXTENSION FOR COMPONENT-LEVEL HETEROGENEOUS DESIGN
- TOWARDS IMPLEMENTING RTL MICROPROCESSOR AGILE DESIGN USING FEATURE ORIENTED PROGRAMMING
- CSLE: A COST-SENSITIVE LEARNING ENGINE FOR DISK FAILURE PREDICTION IN LARGE DATA CENTERS
