なんとなく最近のコンピュータアーキテクチャ系の研究傾向が知りたいので、学会のサーベイをしてみることにした。
次はICCAD。EDAとか半導体設計ツール、半導体設計環境系の話が多いかな。2021年のセッションで興味のありそうなものを引き出してみる。
- ICCAD International Conference on Computer-Aided Design
- Keynote
- Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design
- Challenges and opportunities in GaN power electronics
- RISC-V Is Inevitable
- Designing Reliable Distributed Systems
- 1A. Efficient DNN training and secure/robust DNN inference
- 1B. Advances in Boolean methods for sythesis
- Engineering an Efficient Boolean Functional Synthesis Engine
- Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning
- An Efficient Two-Phase Method for Prime Compilation of NonClausal Boolean Formulae
- Heuristics for Million-scale Two-level Logic Minimization
- 1C. Power model calibration and computing with approximation and uncertainty
- McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs
- Positive/Negative Approximate Multipliers for DNN Accelerators
- MinSC: An Exact Synthesis-Based Method for Minimal Area Stochastic Circuits under Relaxed Error Bound
- CORLD: In-Stream Correlation Manipulation for Low-Discrepancy Stochastic Computing
- 1D. Cross Layer design solutions for energy-efficient and secure edge AI
- TinyML: Massive Opportunity for Edge AI when Machine Intelligence meets the Real World of Billions of Sensors
- Challenges and Opportunities in Security and Reliability of Edge AI
- A General Hardware and Software Co-Design Framework for Energy-Efficient Edge AI
- Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework
- 2A. Efficient DNN inference and tools
- 2B. LOLOL: Lots of logic locking and unlocking
- UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction
- Circuit Deobfuscation from Power Side-Channels using PseudoBoolean SAT
- Exploring eFPGA-based Redaction for IP Protection
- 2C. Quantum CAD matters
- 2D. Multi-Core System design and optimization for the big data era
- BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework
- DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks
- IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs
- Theoretical Analysis and Evaluation of NoCs with Weighted Round Robin Arbitration
- 3A. Algorithm-Hardware co-design for machine learning hardware accelerators
- 3B. Routing with wires and light
- 3C. CAD for novel electronic applications
- 3D. Quantum machine leering: from algorithm to applications
- 4A. Acceleration of emerging deep learning techniques
- 4B. Resilient and efficient embedded applications
- 4C. Simulation and Test generation tools
- Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression
- Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators, Part I: Determining Architectural State Variables
- Machine Learning-Based Test Pattern Generation for Neuromorphic Chips
- Banshee: A Fast LLVM-Based RISC-V Binary Translator
- 4D. VLSI for 5G and beyond wireless in the AI era: Algorithm, hardware and system
- 5A. Hardware software co-design for advanced deep neural networks
- 5B. Security of ML systems
- 5C. Managing complexity with cell design and partitioning
- Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis
- Exploring Physical Synthesis for Circuits based on Emergin Reconfigurable Nanotechnologies
- HyperSF: Spectral Hypergraph Coarsening via Flow-based Local Clustering
- TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA Systems
- 5D. Hardware aware learning for medicine
- 6A. Brain-inspired computing and microfluidic bio-chips
- 6B. New techniques in timing and power analysis
- 6C. Machine learning methods for DFM
- 6D. tutorial: Ferroelectric FET technologies and its applications: from device to system
- Keynote
