なんとなく最近のコンピュータアーキテクチャ系の研究傾向が知りたいので、学会のサーベイをしてみることにした。
ICCADの続き。
- 7A. In-memory computing circuits and architectures
- 7B. Techniques towards fully automated analog IC designs
- 7C. Special sessions: Big Data, Big deal: Data analysis and smart tuning of EDA flows
- 7D. Tutorial: A quantum machine learning co-design framework towards quantum advantage
- 8A. Acceleration methodologies for reconfigurable computing
- Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs
- GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs
- Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization
- DALTA: A Decomposition-based Approximate Lookup Table Architecture
- 8B. SoC Security
- 8C. Placement techniques for advanced VLSI technologies
- 8D. Hardware/software co-design for neuromorphic computing
- 9A. System-level optimization of machine learning applications execution on heterogeneous computing systems
- 9B. Computing to your chips: NVM & Optical interconnects
- NVM (Non-volatile memory: 不揮発性メモリ)
- 9C. Clock tree synthesis, placement, and routing - How to get the best results from the backend of the flow
- 9D. Special session: Brain-inspired computing: Adventure from beyond CMOS technologies to beyond Von Neumann architectures
- 10A. Pushing the boundaries of machine learning and synthesis
- 10B. Hardware approaches for embedded performance and robustness
- Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs
- Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems
- dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference
- Improving the Robustness of Redundant Execution with Register File Randomization
- 10C. Advanced design verification methods
- Bounded Model Checking of Speculative Non-Interference
- Compatible Equivalence Checking of X-Valued Circuits
- Feedback-Guided Circuit Structure Mutation for Testing Hardware Model Checkers
- AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow
- 10D. Security closure of physical layouts
- 11A. Harnessing the power of machine learning: EDA to accelerator design
- VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis
- Optimizing VLSI Implementation with Reinforcement Learning
- Heterogeneous Manycore Architectures Enabled by Processing-in-Memory for Deep Learning: From CNNs to GNNs
- 11B. Parallel power grid solver and geometry-based techniques for analog circuit design
- 11C. Reliability: From interconnects to systems
- 11D. 2021 CAD contest at ICCAD
