DATE 2022
13.3 Advances in permanent storage efficiency and NN-in-memory
- ROBUST BINARY NEURAL NETWORK AGAINST NOISY ANALOG COMPUTATION
- MU-RMW: MINIMIZING UNNECESSARY RMW OPERATIONS IN THE EMBEDDED FLASH WITH SMR DISK
- OPTIMIZING COW-BASED FILE SYSTEMS ON OPEN-CHANNEL SSDS WITH PERSISTENT MEMORY
- MCMQ: SIMULATION FRAMEWORK FOR SCALABLE MULTI-CORE FLASH FIRMWARE OF MULTI-QUEUE SSDS
13.4 System-level security
- CR-SPECTRE: DEFENSE-AWARE ROP INJECTED CODE-REUSE BASED DYNAMIC SPECTRE
- CACHEREWINDER: REVOKING SPECULATIVE CACHE UPDATES EXPLOITING WRITE-BACK BUFFER
- SAFETEE: COMBINING SAFETY AND SECURITY ON ARM-BASED MICROCONTROLLERS
13.5 Safe and Efficient Engineering of Autonomous Systems
- USING ONTOLOGIES FOR DATASET ENGINEERING IN AUTOMOTIVE AI APPLICATIONS
- USING FORMAL CONFORMANCE TESTING TO GENERATE SCENARIOS FOR AUTONOMOUS VEHICLES
- REMOTE SENSING WITH UAV AND MOBILE RECHARGING VEHICLE RENDEZVOUS
17.1 Brain- and Bio-inspired architectures and applications
- ADAPTIVE DROPLET ROUTING FOR MEDA BIOCHIPS VIA DEEP REINFORCEMENT LEARNING
- CONTAMINATION-FREE SWITCH DESIGN AND SYNTHESIS FOR MICROFLUIDIC LARGE-SCALE INTEGRATION
- EXPLOITING PARALLELISM WITH VERTEX-CLUSTERING IN PROCESSING-IN-MEMORY-BASED GCN ACCELERATORS
- ACCELERATING SPATIOTEMPORAL SUPERVISED TRAINING OF LARGE-SCALE SPIKING NEURAL NETWORKS ON GPU
- HYPERSPIKE: HYPERDIMENSIONAL COMPUTING FOR MORE EFFICIENT AND ROBUST SPIKING NEURAL NETWORKS
17.2 Attacks on Secure and Trustworthy Systems
- A DEEP-LEARNING APPROACH TO SIDE-CHANNEL BASED CPU DISASSEMBLY AT DESIGN TIME
- A CROSS-PLATFORM CACHE TIMING ATTACK FRAMEWORK VIA DEEP LEARNING
- DESIGN OF AI TROJANS FOR EVADING MACHINE LEARNING-BASED DETECTION OF HARDWARE TROJANS
- DIP LEARNING ON CAS-LOCK: USING DISTINGUISHING INPUT PATTERNS FOR ATTACKING LOGIC LOCKING
- MUXLINK: CIRCUMVENTING LEARNING-RESILIENT MUX-LOCKING USING GRAPH NEURAL NETWORK-BASED LINK PREDICTION
17.3 Algorithmic techniques for efficient and robust ML hardware
- DTQATTEN: LEVERAGING DYNAMIC TOKEN-BASED QUANTIZATION FOR EFFICIENT ATTENTION ARCHITECTURE
- MIND THE SCALING FACTORS: RESILIENCE ANALYSIS OF QUANTIZED ADVERSARIALLY ROBUST CNNS
- VARIABILITY-AWARE TRAINING AND SELF-TUNING OF HIGHLY QUANTIZED DNNS FOR ANALOG PIM
- CAN DEEP NEURAL NETWORKS BE CONVERTED TO ULTRA LOW-LATENCY SPIKING NEURAL NETWORKS?
- VALUE-AWARE PARITY INSERTION ECC FOR FAULT-TOLERANT DEEP NEURAL NETWORK
17.4 Energy Efficiency with Emerging Technologies for the Edge and the Cloud
- A PRECISION-SCALABLE ENERGY-EFFICIENT BIT-SPLIT-AND-COMBINATION VECTOR SYSTOLIC ACCELERATOR FOR NAS-OPTIMIZED DNNS ON EDGE
- TERNARIZED TCN FOR μJ/INFERENCE GESTURE RECOGNITION FROM DVS EVENT FRAMES
- REH: REDESIGNING EXTENDIBLE HASHING FOR COMMERCIAL NON-VOLATILE MEMORY
- MEMORY MANAGEMENT METHODOLOGY FOR APPLICATION DATA STRUCTURE REFINEMENT AND PLACEMENT ON HETEROGENEOUS DRAM/NVM SYSTEMS
- MICROFAAS: ENERGY-EFFICIENT SERVERLESS ON BARE-METAL SINGLE-BOARD COMPUTERS
17.5 Putting Place and Route research on the right track
- FASTGR : GLOBAL ROUTING ON CPU-GPU WITH HETEROGENEOUS TASK GRAPH SCHEDULER
- TRADER: A PRACTICAL TRACK-ASSIGNMENT-BASED DETAILED ROUTER
- CR&P: AN EFFICIENT CO-OPERATION BETWEEN ROUTING AND PLACEMENT
- PIN ACCESSIBILITY-DRIVEN PLACEMENT OPTIMIZATION WITH ACCURATE AND COMPREHENSIVE PREDICTION MODEL
- MIXED-CELL-HEIGHT LEGALIZATION ON CPU-GPU HETEROGENEOUS SYSTEMS
18.1 Domain-specific co-design: From sensors to graph analytics
- SNE: AN ENERGY-PROPORTIONAL DIGITAL ACCELERATOR FOR SPARSE EVENT-BASED CONVOLUTIONS
- LRP: PREDICTIVE OUTPUT ACTIVATION BASED ON SVD APPROACH FOR CNNS ACCELERATION
- EXPLOITING ARCHITECTURE ADVANCES FOR SPARSE SOLVERS IN CIRCUIT SIMULATION
- DATA-AWARE CACHE MANAGEMENT FOR GRAPH ANALYTICS
- AGAPE: ANOMALY DETECTION WITH GENERATIVE ADVERSARIAL NETWORK FOR IMPROVED PERFORMANCE, ENERGY, AND SECURITY IN MANYCORE SYSTEMS
18.2 Memory-centric and neural network systems: architectures, tools, and profilers
- PIMPROF: AN AUTOMATED PROGRAM PROFILER FOR PROCESSING-IN-MEMORY OFFLOADING DECISIONS
- ANALYSIS OF POWER-ORIENTED FAULT INJECTION ATTACKS ON SPIKING NEURAL NETWORKS
- GIBBON: EFFICIENT CO-EXPLORATION OF NN MODEL AND PROCESSING-IN-MEMORY ARCHITECTURE
- AID: ACCURACY IMPROVEMENT OF ANALOG DISCHARGE-BASED IN-SRAM MULTIPLICATION ACCELERATOR
18.3 Persistent Memory
- CHARACTERIZING AND OPTIMIZING HYBRID DRAM-PM MAIN MEMORY SYSTEM WITH APPLICATION AWARENESS
- PATS: TAMING BANDWIDTH CONTENTION BETWEEN PERSISTENT AND DYNAMIC MEMORIES
- UNIFYING TEMPORAL AND SPATIAL LOCALITY FOR CACHE MANAGEMENT INSIDE SSDS
- DWR: DIFFERENTIAL WEARING FOR READ PERFORMANCE OPTIMIZATION ON HIGH-DENSITY NAND FLASH MEMORY
- GATLB: A GRANULARITY-AWARE TLB TO SUPPORT MULTI-GRANULARITY PAGES IN HYBRID MEMORY SYSTEM
18.4 Energy Efficient Platforms: from Autonomous Vehicles to Intermittent Computing
- OMU: A PROBABILISTIC 3D OCCUPANCY MAPPING ACCELERATOR FOR REAL-TIME OCTOMAP AT THE EDGE
- AN FPGA OVERLAY FOR EFFICIENT REAL-TIME LOCALIZATION IN 1/10TH SCALE AUTONOMOUS VEHICLES
- ENABLING FAST DEEP LEARNING ON TINY ENERGY-HARVESTING IOT DEVICES
- EMULATION OF NON-VOLATILE DIGITAL LOGIC FOR BATTERYLESS INTERMITTENT COMPUTING
18.5 Circuit Optimization and Analysis: No Time to Lose
- A SYSTEMATIC REMOVAL OF MINIMUM IMPLANT AREA VIOLATIONS UNDER TIMING CONSTRAINT
- DREAMPLACE 4.0: TIMING-DRIVEN GLOBAL PLACEMENT WITH MOMENTUM-BASED NET WEIGHTING
- EVENTTIMER: FAST AND ACCURATE EVENT-BASED DYNAMIC TIMING ANALYSIS
- PRACTICAL SUBSTRATE DESIGN CONSIDERING SYMMETRICAL AND SHIELDING ROUTES
19.1 Hardware security primitives and attacks
- ADD-BASED SPECTRAL ANALYSIS OF PROBING SECURITY
- GUARANTEED ACTIVATION OF CAPACITIVE TROJAN TRIGGERS DURING POST PRODUCTION TEST VIA SUPPLY PULSING
- FPGA-TO-CPU UNDERVOLTING ATTACKS
- BEWARE OF THE BIAS - STATISTICAL PERFORMANCE EVALUATION OF HIGHER-ORDER ALPHABET PUFS
19.2 Hardware components and architectures for Machine Learning
- DESIGN OF MANY-CORE BIG LITTLE μBRAINS FOR ENERGY-EFFICIENT EMBEDDED NEUROMORPHIC COMPUTING
- HYDRA: A NEAR HYBRID MEMORY ACCELERATOR FOR CNN INFERENCE
- TCX: A PROGRAMMABLE TENSOR PROCESSOR
- A FLASH-BASED CURRENT-MODE IC TO REALIZE QUANTIZED NEURAL NETWORKS
19.3 NoC optimization with emerging technologies
- NOCEPTION: A FAST PPA PREDICTION FRAMEWORK FOR NETWORK-ON-CHIPS USING GRAPH NEURAL NETWORK
- AN EASY-TO-IMPLEMENT AND EFFICIENT FLOW CONTROL FOR DEADLOCK-FREE ADAPTIVE ROUTING
- DEFT: A DEADLOCK-FREE AND FAULT-TOLERANT ROUTING ALGORITHM FOR 2.5D CHIPLET NETWORKS
- NON-VOLATILE PHASE CHANGE MATERIAL BASED NANOPHOTONIC INTERCONNECT
19.4 Emerging devices for new computing paradigms
- A RELIABILITY CONCERN ON PHOTONIC NEURAL NETWORKS
- HOW PARALLEL CIRCUIT EXECUTION CAN BE USEFUL FOR NISQ COMPUTING?
- SPACE AND POWER REDUCTION IN BDD-BASED OPTICAL LOGIC CIRCUITS EXPLOITING DUAL PORTS
- DESIGN AND EVALUATION FRAMEWORKS FOR ADVANCED RISC-BASED TERNARY PROCESSOR
19.5 Dealing with Correct Design and Robustness analysis for Complex Systems, MPSoCs and Circuits
- REVISITING PASS-TRANSISTOR LOGIC STYLES IN A 12NM FINFET TECHNOLOGY NODE
- SAFESU-2: A SAFE STATISTICS UNIT FOR SPACE MPSOCS
- EFFICIENT GLOBAL ROBUSTNESS CERTIFICATION OF NEURAL NETWORKS VIA INTERLEAVING TWIN-NETWORK ENCODING
- OPPORTUNISTIC COMMUNICATION WITH LATENCY GUARANTEES FOR INTERMITTENTLY-POWERED DEVICES
21.1 Self-adaptive and Dynamic Resource Management, Learning at the Edge and Applications
- ACCURATE PROBABILISTIC MISS RATIO CURVE APPROXIMATION FOR ADAPTIVE CACHE ALLOCATION IN BLOCK STORAGE SYSTEMS
- SGRM: STACKELBERG GAME-BASED RESOURCE MANAGEMENT FOR EDGE COMPUTING SYSTEMS
- RUNTIME ENERGY MINIMIZATION OF DISTRIBUTED MANY-CORE SYSTEMS USING TRANSFER LEARNING
- SIAMESE NEURAL ENCODERS FOR LONG-TERM INDOOR LOCALIZATION WITH MOBILE DEVICES
- DISCRETE SAMPLERS FOR APPROXIMATE INFERENCE IN PROBABILISTIC MACHINE LEARNING
- HELCFL: HIGH-EFFICIENCY AND LOW-COST FEDERATED LEARNING IN HETEROGENEOUS MOBILE-EDGE COMPUTING
21.2 Advances in defect detection and dependability
- HOTSPOT DETECTION VIA GRAPH NEURAL NETWORK
- FITACT: ERROR RESILIENT DEEP NEURAL NETWORKS VIA FINE-GRAINED POST-TRAINABLE ACTIVATION FUNCTIONS
- WRAP: WEIGHT REMAPPING AND PROCESSING IN RRAM-BASED NEURAL NETWORK ACCELERATORS CONSIDERING THERMAL EFFECT
- SELF-TERMINATED WRITE OF MULTI-LEVEL CELL RERAM FOR EFFICIENT NEUROMORPHIC COMPUTING
- SCLCRL: SHUTTLING C-ELEMENTS BASED LOW-COST AND ROBUST LATCH DESIGN PROTECTED AGAINST TRIPLE NODE UPSETS IN HARSH RADIATION ENVIRONMENTS
- LEAKAGE POWER ANALYSIS IN DIFFERENT S-BOX MASKING PROTECTION SCHEMES
21.3 Real-Time Systems and Technology
- CACHE-AWARE SCHEDULABILITY ANALYSIS OF PREM COMPLIANT TASKS
- RECONCILING QOS AND CONCURRENCY IN NVIDIA GPUS VIA WARP-LEVEL SCHEDULING
- COUNTING PRIORITY INVERSIONS: COMPUTING MAXIMUM ADDITIONAL CORE REQUESTS OF DAG TASKS
- SHYPER: AN EMBEDDED HYPERVISOR APPLYING HIERARCHICAL RESOURCE ISOLATION STRATEGIES FOR MIXED-CRITICALITY SYSTEMS
- RESPONSE TIME ANALYSIS FOR ENERGY-HARVESTING MIXED-CRITICALITY SYSTEMS
- LATENCY ANALYSIS OF SELF-SUSPENDING TASK CHAINS
21.4 Defense Techniques for Secure and Trustworthy Systems
- COUNTERACT SIDE-CHANNEL ANALYSIS OF NEURAL NETWORKS BY SHUFFLING
- GNN4GATE: A BI-DIRECTIONAL GRAPH NEURAL NETWORK FOR GATE-LEVEL HARDWARE TROJAN DETECTION
- GOLDEN MODEL-FREE HARDWARE TROJAN DETECTION BY CLASSIFICATION OF NETLIST MODULE GRAPHS
- JANUS-HD: EXPLOITING FSM SEQUENTIALITY AND SYNTHESIS FLEXIBILITY IN LOGIC OBFUSCATION TO THWART SAT ATTACK WHILE OFFERING STRONG CORRUPTION
- TRILOCK: IC PROTECTION WITH TUNABLE CORRUPTIBILITY AND RESILIENCE TO SAT AND REMOVAL ATTACKS
22.1 Heterogeneous system-on-chip design methods
- UNDERSTANDING AND MITIGATING MEMORY INTERFERENCE IN FPGA-BASED HESOCS
- POWERGEAR: EARLY-STAGE POWER ESTIMATION IN FPGA HLS VIA HETEROGENEOUS EDGE-CENTRIC GNNS
- ENERGY EFFICIENT, REAL-TIME AND RELIABLE TASK DEPLOYMENT ON NOC-BASED MULTICORES WITH DVFS
- COXHE: A SOFTWARE-HARDWARE CO-DESIGN FRAMEWORK FOR FPGA ACCELERATION OF HOMOMORPHIC COMPUTATION
- A COMPOSABLE DESIGN SPACE EXPLORATION FRAMEWORK TO OPTIMIZE BEHAVIORAL LOCKING
22.2 Power, Thermal and Performance Management for Advanced Computing Systems
- DIET: A DYNAMIC ENERGY MANAGEMENT APPROACH FOR WEARABLE HEALTH MONITORING DEVICES
- IMPROVE THE STABILITY AND ROBUSTNESS OF POWER MANAGEMENT THROUGH MODEL-FREE DEEP REINFORCEMENT LEARNING
- COREMEMDTM: INTEGRATED PROCESSOR CORE AND 3D MEMORY DYNAMIC THERMAL MANAGEMENT FOR IMPROVED PERFORMANCE
- THERMAL- AND CACHE-AWARE RESOURCE MANAGEMENT BASED ON ML-DRIVEN CACHE CONTENTION PREDICTION
- T-SKID: PREDICTING WHEN TO PREFETCH SEPARATELY FROM ADDRESS PREDICTION
