フロントエンドの，デコーダの部分が非常に重たい．
Slack (VIOLATED) : -17.096ns (required time - arrival time)
Source: u_scariv_tile/u_frontend/u_scariv_inst_buffer/u_inst_queue/r_outptr_reg[1]/C
(rising edge-triggered cell FDCE clocked by i_clk {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_scariv_tile/u_frontend/u_scariv_inst_buffer/o_decode_flush_reg[valid]_bret/D
(rising edge-triggered cell FDCE clocked by i_clk {rise@0.000ns fall@5.000ns period=10.000ns})
これはもう一度書き直したほうがいいかもしれないと思いだした． 問題はRVCの判定から命令の切り出しの処理まで全部を1サイクルでやろうとしていることと，どうも不正確なフィードバックループが入っているような気がして，短縮できるような気がする．
やはりRVCを切り出してから，キャッシュラインの中でディスパッチにもっていく最大命令を引き出すあたりが長いパスにつながっている． 次のデコードがキャッシュライン内のどこから始まるのかを選定する部分が大きいのか． これはどうやって解決するかな．．．
LUT5 (Prop_lut5_I0_O) 0.097 18.919 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/word_loop[3].u_decoder_inst_cat/u_inst/inst_cat[1]_INST_0/O
net (fo=10, unplaced) 0.554 19.473 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/w_inst_cat[3][1]
LUT6 (Prop_lut6_I3_O) 0.097 19.570 f u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_illegal_disp_pick_up_i_1/O
net (fo=1, unplaced) 0.301 19.871 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_illegal_disp_pick_up/in[3]
LUT4 (Prop_lut4_I3_O) 0.097 19.968 f u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_illegal_disp_pick_up/out[3]_INST_0/O
net (fo=2, unplaced) 0.312 20.280 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/w_inst_illegal_disp[3]
LUT6 (Prop_lut6_I5_O) 0.097 20.377 f u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_inst_msb_i_7/O
net (fo=1, unplaced) 0.301 20.678 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_inst_msb_i_7_n_0
LUT5 (Prop_lut5_I4_O) 0.097 20.775 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_inst_msb_i_1/O
net (fo=1, unplaced) 0.301 21.076 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_inst_msb/u_bit_tree/in[3]
LUT4 (Prop_lut4_I1_O) 0.097 21.173 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_inst_msb/u_bit_tree/out[3]_INST_0/O
net (fo=1, unplaced) 0.301 21.474 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_inst_msb/tree[3]
LUT2 (Prop_lut2_I1_O) 0.097 21.571 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_inst_msb/out[3]_INST_0/O
net (fo=1, unplaced) 0.301 21.872 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/w_inst_disp_mask_tmp[3]
LUT4 (Prop_lut4_I2_O) 0.097 21.969 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_special_valid_lsb_i_5/O
net (fo=3, unplaced) 0.319 22.288 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_special_valid_lsb_i_5_n_0
LUT3 (Prop_lut3_I0_O) 0.097 22.385 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_special_valid_lsb_i_1/O
net (fo=1, unplaced) 0.301 22.686 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_special_valid_lsb/u_bit_tree/in[3]
LUT4 (Prop_lut4_I1_O) 0.097 22.783 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_special_valid_lsb/u_bit_tree/out[3]_INST_0/O
net (fo=1, unplaced) 0.301 23.084 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_special_valid_lsb/tree[3]
LUT2 (Prop_lut2_I1_O) 0.097 23.181 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_special_valid_lsb/out[3]_INST_0/O
net (fo=2, unplaced) 0.312 23.493 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/w_disp_special_limit_valid_oh[3]
LUT6 (Prop_lut6_I5_O) 0.097 23.590 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/ibuf_front_if\\.payload[inst][3][valid]_i_7/O
net (fo=4, unplaced) 0.325 23.915 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/ibuf_front_if\\.payload[inst][3][valid]_i_7_n_0
LUT3 (Prop_lut3_I1_O) 0.097 24.012 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_start_pos_bit_i_13/O
net (fo=2, unplaced) 0.312 24.324 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_start_pos_bit_i_13_n_0
LUT6 (Prop_lut6_I5_O) 0.097 24.421 f u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_start_pos_bit_i_4/O
net (fo=146, unplaced) 0.620 25.041 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_start_pos_bit_i_4_n_0
LUT6 (Prop_lut6_I3_O) 0.097 25.138 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush[valid]_bret__2_bret__0_i_1/O
net (fo=22, unplaced) 0.902 26.040 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush[valid]_bret__2_bret__0_i_1_n_0
LUT5 (Prop_lut5_I0_O) 0.097 26.137 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_ras_i_2/O
net (fo=38, unplaced) 0.376 26.513 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_ras/i_f2_rd_valid
LUT6 (Prop_lut6_I0_O) 0.097 26.610 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/u_ras/o_f2_rd_pa[3]_INST_0/O
net (fo=9, unplaced) 0.552 27.162 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/w_iq_ras_ret_vaddr[3]
LUT6 (Prop_lut6_I1_O) 0.097 27.259 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush[valid]_bret_i_35/O
net (fo=1, unplaced) 0.000 27.259 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush[valid]_bret_i_35_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.412 27.671 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush_reg[valid]_bret_i_28/CO[3]
net (fo=1, unplaced) 0.007 27.678 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush_reg[valid]_bret_i_28_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.089 27.767 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush_reg[valid]_bret_i_19/CO[3]
net (fo=1, unplaced) 0.000 27.767 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush_reg[valid]_bret_i_19_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.089 27.856 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush_reg[valid]_bret_i_12/CO[3]
net (fo=1, unplaced) 0.000 27.856 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush_reg[valid]_bret_i_12_n_0
CARRY4 (Prop_carry4_CI_CO[0])
0.223 28.079 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush_reg[valid]_bret_i_6/CO[0]
net (fo=1, unplaced) 0.208 28.287 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush_reg[valid]_bret_i_6_n_3
LUT2 (Prop_lut2_I0_O) 0.262 28.549 f u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush[valid]_bret_i_3/O
net (fo=1, unplaced) 0.301 28.850 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush[valid]_bret_i_3_n_0
LUT6 (Prop_lut6_I3_O) 0.097 28.947 r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush[valid]_bret_i_1/O
net (fo=1, unplaced) 0.000 28.947 u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush[valid]_bret_i_1_n_0
FDCE r u_mycpu_tile/u_frontend/u_mycpu_inst_buffer/o_decode_flush_reg[valid]_bret/D
