CHANGESは以下の通り。これを見る限りあまり大きな変更はないように思える。 自分の自作CPUをアップデートして、試してみなければ。
[> Fixed -------- - liteeth/arp : Fixed response on table update. - litesata/us(p)sataphy : Fixed data_width=32 case. - clock/lattice_ecp5 : Fixed phase calculation. - interconnect/axi : Fixed AXILite2CSR read access (1 CSR cycle instead of 2). [> Added -------- - cpu/naxriscv : Added SMP support. - cpu/neorv32 : Added Debug support and update core complex. - cpu/vexriscv_smp : Added hardware breakpoints support. - build/colognechip : Added initial support. - soc/cores/video : Added VTG/DMA synchronization stage to VideoFramebuffer. - litepcie/dma : Improved LitePCIeDMADescriptorSplitter timings. - interconnect/wishbone : Added linear burst support to DownConverter. - integration/SoC : Added with_jtagbone/with_uartbone support. - soc/cores : Added Ti60F100 HyperRAM support. - build/xilinx : Added initial OpenXC7 support (and improved Yosys-NextPnr). - build/efinix : Added JTAG-UART/JTAGBone support. - interconnect/wishbone : Added byte/word addressing support. - cores/uart : Added 64-bit addressing support to Stream2Wishbone. - tools : Added 64-bit addressing support to litex_server/client. - cores/cpu : Added 64-bit support to CPUNone. - cores/cpu : Added KianV (RV32IMA) initial support. - litedram : Added initial GW5DDRPHY (compiles but not yet working). - build/gowin : Added GowinTristate implementation. - litepcie : Simplify/Cleanup Ultrascale(+) integration and allow .xci generation from .tcl. - litepcie : Initial 64-bit DMA suppport. - bios : Added bios_format / --bios-format to allow enabling float/double printf. - soc/cores/clock : Added proper clock feedback support on Efinix TRIONPLL/TITANIUMPLL. - liteiclink/phy : Added Efinix support/examples on Trion/Titanium. - liteiclink/serwb : Reused Etherbone from LiteEth to avoid code duplication. - interconnect : Added 64-bit support to Wishbone/AXI-Lite/AXI. - jtag : Fixed firmware upload over JTAG-UART. - jtag : Improved speed (~X16) on JTABone/JTAGUART on all supported devices (Xilinx, Altera, Efinix, etc...) - litesata/phy : Added GTHE4 support on Ultrascale+. - litex_boards : Added Machdyne's Mozart with the Sechzig ML1 module support. - liteiclink : Added clk_ratio of 1:2, 1:4 on Efinix/SerWB to make clocking more flexible. [> Changed ---------- - build/osfpga : Removed initial support (would need feedbacks/updates). - python3 : Updated minimum python3 version to 3.7 (To allow more than 255 arguments in functions).
