LiteXの合成環境を使って、各種コアの動作周波数とサイズを見積もった時のメモ。tag 2023.8でRocketが合成できなくなってしまっていた。
- VexRiscv
python3 -m litex_boards.targets.digilent_zedboard --cpu-type=vexriscv --build
- 論理合成結果： VexRiscvって小さいんだな。
+-------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------------+------+-------+------------+-----------+-------+ | Slice LUTs | 2089 | 0 | 0 | 53200 | 3.93 | | LUT as Logic | 2089 | 0 | 0 | 53200 | 3.93 | | LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 | | Slice Registers | 1610 | 0 | 0 | 106400 | 1.51 | | Register as Flip Flop | 1610 | 0 | 0 | 106400 | 1.51 | | Register as Latch | 0 | 0 | 0 | 106400 | 0.00 | | F7 Muxes | 0 | 0 | 0 | 26600 | 0.00 | | F8 Muxes | 0 | 0 | 0 | 13300 | 0.00 | +-------------------------+------+-------+------------+-----------+-------+ * Warning! LUT value is adjusted to account for LUT combining.
- 周波数制約
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
1.219 0.000 0 4110 0.102 0.000 0 4110 3.000 0.000 0 1648
All user specified timing constraints are met.
- NaxRiscv
python3 -m litex_boards.targets.digilent_zedboard --cpu-type=naxriscv --build
- 論理合成結果： それでも小さくてZedBoardでも余裕で収まるんだね。
+----------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------------------+-------+-------+------------+-----------+-------+ | Slice LUTs | 13308 | 0 | 0 | 53200 | 25.02 | | LUT as Logic | 9949 | 0 | 0 | 53200 | 18.70 | | LUT as Memory | 3359 | 0 | 0 | 17400 | 19.30 | | LUT as Distributed RAM | 3334 | 0 | | | | | LUT as Shift Register | 25 | 0 | | | | | Slice Registers | 8458 | 0 | 0 | 106400 | 7.95 | | Register as Flip Flop | 8458 | 0 | 0 | 106400 | 7.95 | | Register as Latch | 0 | 0 | 0 | 106400 | 0.00 | | F7 Muxes | 176 | 0 | 0 | 26600 | 0.66 | | F8 Muxes | 1 | 0 | 0 | 13300 | <0.01 | +----------------------------+-------+-------+------------+-----------+-------+ * Warning! LUT value is adjusted to account for LUT combining.
- 周波数制約
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.116 0.000 0 49311 0.018 0.000 0 49311 3.000 0.000 0 13198
All user specified timing constraints are met.
Rocketは論理合成試行時にエラーになってしまった。
/home/msyksphinz/work/riscv/litex/litex_scariv/litex/litex/soc/software/libbase/isr.c: In function 'isr':
/home/msyksphinz/work/riscv/litex/litex_scariv/litex/litex/soc/software/libbase/isr.c:58:22: error: 'UART_INTERRUPT' undeclared (first use in this function); did you mean 'TIMER0_INTERRUPT'?
58 | case UART_INTERRUPT:
| ^~~~~~~~~~~~~~
| TIMER0_INTERRUPT
/home/msyksphinz/work/riscv/litex/litex_scariv/litex/litex/soc/software/libbase/isr.c:58:22: note: each undeclared identifier is reported only once for each function it appears in
make: *** [/home/msyksphinz/work/riscv/litex/litex_scariv/litex/litex/soc/software/libbase/Makefile:25: isr.o] Error 1
make: Leaving directory '/home/msyksphinz/work/riscv/litex/litex_vexriscv/build_naxriscv/software/libbase'
Traceback (most recent call last):
File "/home/msyksphinz/mambaforge/lib/python3.10/runpy.py", line 196, in _run_module_as_main
return _run_code(code, main_globals, None,
