Universal Hardware Data Model (UHDM) に関する情報を調べる (3. サンプルデザインで確かめる)

UHDMというのは、ハードウェアを表現するためのデータモデルで、YAML形式で表現されている。 私の持っている一番汎用的な書き方をしているモジュールが、どのようにUHDMで表現されるのか見てみることにした。

module bit_oh_or_packed
  #(
    parameter type T = logic[31: 0],
    parameter WORDS = 4
  )
(
  input logic [WORDS-1:0] i_oh,
  input T [WORDS-1:0]     i_data,
  output T                o_selected
);

T w_data[WORDS];
generate for (genvar i = 0; i < WORDS; i++) begin
  assign w_data[i] = i_data[i];
end
endgenerate

bit_oh_or #(.T(T), .WORDS(WORDS))
u_inst (.i_oh(i_oh), .i_data(w_data), .o_selected(o_selected));

endmodule

• 入力の型がTで汎用化されている。
• エントリの数がWORDSで汎用化されている。
• 中でgenerateを使っている。

変換すると以下のようになった。

$ surelog/Surelog/dbuild/bin/surelog -parse bit_oh_or_packed.sv
$ surelog/Surelog/dbuild/third_party/UHDM/bin/uhdm-dump slpp_all/surelog.uhdm | less

• 最初の階層

|vpiName:work@bit_oh_or_packed
|uhdmallPackages:
\_package: builtin (builtin::), file:, parent:work@bit_oh_or_packed
|uhdmtopPackages:
\_package: builtin (builtin::), file:, parent:work@bit_oh_or_packed
|uhdmallClasses:
\_class_defn: (work@mailbox), file:builtin.sv, parent:work@bit_oh_or_packed
|uhdmallClasses:
\_class_defn: (work@process), file:builtin.sv, parent:work@bit_oh_or_packed
|uhdmallClasses:
\_class_defn: (work@semaphore), file:builtin.sv, parent:work@bit_oh_or_packed
|uhdmallModules:
\_module: work@bit_oh_or_packed (work@bit_oh_or_packed) bit_oh_or_packed.sv:1:1: , endln:21:10, parent:work@bit_oh_or_packed
|uhdmtopModules:
\_module: work@bit_oh_or_packed (work@bit_oh_or_packed) bit_oh_or_packed.sv:1:1: , endln:21:10

この中だとuhdmAllModulesが必要な情報かな？

• type_parameterの定義

  |vpiParameter:
  \_type_parameter: (work@bit_oh_or_packed.T), line:3:20, endln:3:21, parent:work@bit_oh_or_packed
    |vpiName:T
    |vpiFullName:work@bit_oh_or_packed.T
    |vpiTypespec:
    \_logic_typespec: , line:3:24, endln:3:29, parent:work@bit_oh_or_packed.T
      |vpiRange:
      \_range: , line:3:30, endln:3:35, parent:work@bit_oh_or_packed.T
        |vpiLeftRange:
        \_constant: , line:3:30, endln:3:32
          |vpiDecompile:31
          |vpiSize:64
          |UINT:31
          |vpiConstType:9
        |vpiRightRange:
        \_constant: , line:3:34, endln:3:35
          |vpiDecompile:0
          |vpiSize:64
          |UINT:0
          |vpiConstType:9

• 普通のparameterの定義

  |vpiParameter:
  \_parameter: (work@bit_oh_or_packed.WORDS), line:4:15, endln:4:20, parent:work@bit_oh_or_packed
    |UINT:4
    |vpiTypespec:
    \_int_typespec:
    |vpiName:WORDS
    |vpiFullName:work@bit_oh_or_packed.WORDS
  |vpiParamAssign:
  \_param_assign: , line:4:15, endln:4:24, parent:work@bit_oh_or_packed
    |vpiRhs:
    \_constant: , line:4:23, endln:4:24
      |vpiDecompile:4
      |vpiSize:32
      |UINT:4
      |vpiTypespec:
      \_int_typespec:
      |vpiConstType:9
    |vpiLhs:
    \_parameter: (work@bit_oh_or_packed.WORDS), line:4:15, endln:4:20, parent:work@bit_oh_or_packed

• 内部ネットの定義 : vpiNetで定義するらしい。

  |vpiNet:
  \_logic_net: (work@bit_oh_or_packed.i_oh), line:7:27, endln:7:31, parent:work@bit_oh_or_packed
    |vpiName:i_oh
    |vpiFullName:work@bit_oh_or_packed.i_oh
    |vpiNetType:36
  |vpiNet:
  \_logic_net: (work@bit_oh_or_packed.i_data), line:8:27, endln:8:33, parent:work@bit_oh_or_packed
    |vpiName:i_data
    |vpiFullName:work@bit_oh_or_packed.i_data
  |vpiNet:
  \_logic_net: (work@bit_oh_or_packed.o_selected), line:9:27, endln:9:37, parent:work@bit_oh_or_packed
    |vpiName:o_selected
    |vpiFullName:work@bit_oh_or_packed.o_selected
  |vpiNet:
  \_logic_net: (work@bit_oh_or_packed.w_data), line:12:3, endln:12:9, parent:work@bit_oh_or_packed
    |vpiName:w_data
    |vpiFullName:work@bit_oh_or_packed.w_data

• ポートの定義 : vpiPortで定義するらしい

  |vpiPort:
  \_port: (i_oh), line:7:27, endln:7:31, parent:work@bit_oh_or_packed
    |vpiName:i_oh
    |vpiDirection:1
    |vpiLowConn:
    \_ref_obj:
      |vpiActual:
      \_logic_net: (work@bit_oh_or_packed.i_oh), line:7:27, endln:7:31, parent:work@bit_oh_or_packed
  |vpiPort:
  \_port: (i_data), line:8:27, endln:8:33, parent:work@bit_oh_or_packed
    |vpiName:i_data
    |vpiDirection:1
    |vpiLowConn:
    \_ref_obj:
      |vpiActual:
      \_logic_net: (work@bit_oh_or_packed.i_data), line:8:27, endln:8:33, parent:work@bit_oh_or_packed
  |vpiPort:
  \_port: (o_selected), line:9:27, endln:9:37, parent:work@bit_oh_or_packed
    |vpiName:o_selected
    |vpiDirection:2
    |vpiLowConn:
    \_ref_obj:
      |vpiActual:
      \_logic_net: (work@bit_oh_or_packed.o_selected), line:9:27, endln:9:37, parent:work@bit_oh_or_packed

generateの部分は、とりあえずパラメータの通りにfor文を崩して展開するらしい。

  |vpiGenScopeArray:
  \_gen_scope_array: (work@bit_oh_or_packed.genblk1[0]), line:13:45, endln:15:4, parent:work@bit_oh_or_packed
    |vpiName:genblk1[0]
    |vpiFullName:work@bit_oh_or_packed.genblk1[0]
--
  |vpiGenScopeArray:
  \_gen_scope_array: (work@bit_oh_or_packed.genblk1[1]), line:13:45, endln:15:4, parent:work@bit_oh_or_packed
    |vpiName:genblk1[1]
    |vpiFullName:work@bit_oh_or_packed.genblk1[1]
--
  |vpiGenScopeArray:
  \_gen_scope_array: (work@bit_oh_or_packed.genblk1[2]), line:13:45, endln:15:4, parent:work@bit_oh_or_packed
    |vpiName:genblk1[2]
    |vpiFullName:work@bit_oh_or_packed.genblk1[2]
--
  |vpiGenScopeArray:
  \_gen_scope_array: (work@bit_oh_or_packed.genblk1[3]), line:13:45, endln:15:4, parent:work@bit_oh_or_packed
    |vpiName:genblk1[3]
    |vpiFullName:work@bit_oh_or_packed.genblk1[3]