VivadoのSynthesisオプションを見て気が付いたのだが，synth_designでは明示的に-retimingオプションを追加しないとレジスタ乗りタイミングをしてくれないらしい．
今の自作CPUの実装では，FPNEWのパイプラインはレジスタのリタイミング機能に依存しているため，これができないと困る．今のクリティカルパスはそこに現れている．
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -5.060ns (required time - arrival time)
Source: scariv_subsystem_axi_wrapper/u_scariv_subsystem/u_tile/fpu.fpu_loop[0].u_fpu/u_fpu/u_scariv_fpnew_wrapper/u_fpnew_top/gen_operation_groups[0].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_fma_multi/gen_input_pipeline[0].inp_pipe_operands_q_reg[1][0][41]/C
(rising edge-triggered cell FDCE clocked by main_crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: scariv_subsystem_axi_wrapper/u_scariv_subsystem/u_tile/fpu.fpu_loop[0].u_fpu/u_fpu/u_scariv_fpnew_wrapper/u_fpnew_top/gen_operation_groups[0].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_fma_multi/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][158]/D
(rising edge-triggered cell FDCE clocked by main_crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
これは，LiteXのスクリプトをそのまま改造して-retimingオプションを追加するしかない気がする．
diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index ed450efbd..eabeb9094 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -287,7 +287,7 @@ class XilinxVivadoToolchain(GenericToolchain):
# Synthesis
if self._synth_mode == "vivado":
tcl.append("\n# Synthesis\n")
- synth_cmd = f"synth_design -directive {self.vivado_synth_directive} -top {self._build_name} -part {self.platform.device}"
+ synth_cmd = f"synth_design -retiming -directive {self.vivado_synth_directive} -top {self._build_name} -part {self.platform.device}"
if self.platform.verilog_include_paths:
synth_cmd += f" -include_dirs {{{' '.join(self.platform.verilog_include_paths)}}}"
tcl.append(synth_cmd)
これでVivadoの合成を再度試行してみよう．
合成結果，クリティカルパスは以下のように改善されたが，どうもこれはリタイミングの影響ではないっぽい．
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -4.508ns (required time - arrival time)
Source: scariv_subsystem_axi_wrapper/u_scariv_subsystem/u_tile/fpu.fpu_loop[0].u_fpu/u_fpu/u_scariv_fpnew_wrapper/u_fpnew_top/gen_operation_groups[0].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_fma_multi/gen_inside_pipeline[1].mid_pipe_sum_q_reg[2][26]/C
(rising edge-triggered cell FDCE clocked by main_crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: scariv_subsystem_axi_wrapper/u_scariv_subsystem/u_tile/fpu.fpu_loop[0].u_fpu/u_fpu/u_scariv_fpnew_wrapper/u_fpnew_top/gen_operation_groups[0].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_fma_multi/gen_output_pipeline[0].out_pipe_status_q_reg[1][NX]/D
(rising edge-triggered cell FDCE clocked by main_crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
