自作CPUコアのVivadoでの論理合成を試行する。
最初にVivadoのバグによって論理合成が進まなくなってしまった。
https://support.xilinx.com/s/article/73178?language=ja
これを修正する必要があった。
commit 9186fa64e6e925c64e13211873517c999d79dfb0
Author: msyksphinz <msyksphinz.dev@gmail.com>
Date: Fri Dec 1 17:38:17 2023 +0900
Fix synthesis Vivado problem in ptw.sv
diff --git a/src/mycore_ptw.sv b/src/mycore_ptw.sv
index 2f8ba3be..8069c2cd 100644
--- a/src/mycore_ptw.sv
+++ b/src/mycore_ptw.sv
@@ -9,7 +9,8 @@
module mycore_ptw
import mycore_lsu_pkg::*;
#(
- localparam PTW_PORT_NUM = 1 + mycore_conf_pkg::LSU_INST_NUM + 1
+ localparam PTW_PORT_NUM = 1 + mycore_conf_pkg::LSU_INST_NUM + 1,
+ parameter dummy = 1
)
(
input logic i_clk,
あとはタイミングループがあったのでそれを修正する。
WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through u_issue_uniti_29/w_picked_inst_locked_oh[0]' WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through u_issue_uniti_29/w_picked_inst_locked_oh[0]' WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through u_issue_uniti_29/w_picked_inst_locked_oh[1]' WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through u_issue_uniti_29/w_picked_inst_locked_oh[1]' WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through u_issue_uniti_29/w_picked_inst_locked_oh[2]' WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through u_issue_uniti_29/w_picked_inst_locked_oh[2]' WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through u_issue_uniti_29/w_picked_inst_locked_oh[3]' WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through u_issue_uniti_29/w_picked_inst_locked_oh[3]'
論理合成の結果を確認する。
- タイミング
Slack (MET) : 0.317ns (required time - arrival time)
Source: u_mycore_tile/u_rob/o_commit_reg[commit]_rep/C
(rising edge-triggered cell FDCE clocked by i_clk {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_mycore_tile/vpu.u_vec_lsu/u_lsu_pipe/r_ex1_replay_selected_reg/D
(rising edge-triggered cell FDRE clocked by i_clk {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: i_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (i_clk rise@10.000ns - i_clk rise@0.000ns)
Data Path Delay: 9.528ns (logic 1.658ns (17.401%) route 7.870ns (82.599%))
Logic Levels: 26 (BUFGCE=1 LUT2=1 LUT3=2 LUT4=3 LUT5=3 LUT6=16)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.927ns = ( 12.927 - 10.000 )
Source Clock Delay (SCD): 3.355ns
Clock Pessimism Removal (CPR): 0.283ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- 面積
+----------------------------+--------+-------+-----------+--------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+--------+-------+-----------+--------+ | CLB LUTs* | 368657 | 0 | 230400 | 160.01 | | LUT as Logic | 366130 | 0 | 230400 | 158.91 | | LUT as Memory | 2527 | 0 | 101760 | 2.48 | | LUT as Distributed RAM | 2372 | 0 | | | | LUT as Shift Register | 155 | 0 | | | | CLB Registers | 180560 | 0 | 460800 | 39.18 | | Register as Flip Flop | 180447 | 0 | 460800 | 39.16 | | Register as Latch | 113 | 0 | 460800 | 0.02 | | CARRY8 | 2333 | 0 | 28800 | 8.10 | | F7 Muxes | 65533 | 0 | 115200 | 56.89 | | F8 Muxes | 28603 | 0 | 57600 | 49.66 | | F9 Muxes | 0 | 0 | 28800 | 0.00 | +----------------------------+--------+-------+-----------+--------+
+------------------------------+--------------------------------------+------------+------------+---------+------+--------+--------+--------+------+--------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | URAM | DSP48 Blocks | +------------------------------+--------------------------------------+------------+------------+---------+------+--------+--------+--------+------+--------------+ | scariv_tile_wrapper | (top) | 368657 | 366130 | 2372 | 155 | 180560 | 24 | 0 | 0 | 95 | | (scariv_tile_wrapper) | (top) | 69 | 69 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | u_scariv_tile | scariv_tile | 368589 | 366062 | 2372 | 155 | 180560 | 24 | 0 | 0 | 95 | | (u_scariv_tile) | scariv_tile | 71 | 71 | 0 | 0 | 7 | 0 | 0 | 0 | 0 | | alu_loop[0].u_alu | scariv_alu | 12950 | 12876 | 0 | 74 | 4689 | 0 | 0 | 0 | 32 | | alu_loop[1].u_alu | scariv_alu__parameterized0 | 14236 | 14162 | 0 | 74 | 4863 | 0 | 0 | 0 | 32 | | fpu.fpu_loop[0].u_fpu | scariv_fpu | 22915 | 22915 | 0 | 0 | 4173 | 0 | 0 | 0 | 9 | | fpu.u_fp_phy_registers | scariv_phy_registers | 5477 | 5477 | 0 | 0 | 4096 | 0 | 0 | 0 | 0 | | u_bru | scariv_bru | 16721 | 16721 | 0 | 0 | 3458 | 0 | 0 | 0 | 0 | | u_csu | scariv_csu | 8925 | 8925 | 0 | 0 | 5706 | 0 | 0 | 0 | 0 | | u_frontend | scariv_frontend | 13276 | 11656 | 1620 | 0 | 14658 | 8 | 0 | 0 | 0 | | u_int_phy_registers | scariv_phy_registers__parameterized0 | 17026 | 17026 | 0 | 0 | 8548 | 0 | 0 | 0 | 0 | | u_lsu_top | scariv_lsu_top | 40637 | 40085 | 552 | 0 | 11716 | 16 | 0 | 0 | 0 | | u_ptw | scariv_ptw | 370 | 370 | 0 | 0 | 92 | 0 | 0 | 0 | 0 | | u_rename | scariv_rename | 22611 | 22611 | 0 | 0 | 10674 | 0 | 0 | 0 | 0 | | u_resource_alloc | scariv_resource_alloc | 306 | 306 | 0 | 0 | 112 | 0 | 0 | 0 | 0 | | u_rob | scariv_rob | 11741 | 11741 | 0 | 0 | 13372 | 0 | 0 | 0 | 0 | | u_snoop_top | scariv_snoop_top | 201 | 201 | 0 | 0 | 750 | 0 | 0 | 0 | 0 | | vpu.u_vec_alu | scariv_vec_alu | 60043 | 60043 | 0 | 0 | 17571 | 0 | 0 | 0 | 22 | | vpu.u_vec_lsu | scariv_vec_lsu | 16572 | 16365 | 200 | 7 | 10370 | 0 | 0 | 0 | 0 | | vpu.u_vec_registers | scariv_vec_registers | 104449 | 104449 | 0 | 0 | 65536 | 0 | 0 | 0 | 0 | | vpu.u_vec_vlvtype_rename | scariv_vec_vlvtype_rename | 62 | 62 | 0 | 0 | 169 | 0 | 0 | 0 | 0 | +------------------------------+--------------------------------------+------------+------------+---------+------+--------+--------+--------+------+--------------+ ベクトル・レジスタの面積が異常に多いな。各レジスタ種類に応じて長さは可変にできるようにしているので、その辺の問題だな。
