シミュレーション環境の調査を行うために、gdbを当ててみた。
$ cd ./build/sim/gateware/
$ gdb ./obj_dir/Vsim
run
これで一応挙動をチェックできる。
__ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2022 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Dec 27 2022 00:53:25 BIOS CRC passed (97c80175) LiteX git sha1: 84a65f36 --=============== SoC ==================-- CPU: VexRiscv SMP-LINUX @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB SDRAM: 65536KiB 32-bit @ 100MT/s (CL-2 CWL-2) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Program received signal SIGINT, Interrupt. Vsim_VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood___sequent__TOP__sim__VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood__3 (vlSelf=vlSelf@entry=0x7ffff79a3280) at Vsim_VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood__DepSet_he9900fa0__0.cpp:4292 4292 if (((~ (IData)(vlSelf->__PVT__iBridge_logic__DOT__cmdFork_ready)) (gdb) bt #0 Vsim_VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood___sequent__TOP__sim__VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood__3 (vlSelf=vlSelf@entry=0x7ffff79a3280) at Vsim_VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood__DepSet_he9900fa0__0.cpp:4292 #1 0x00005555555e6c1f in Vsim___024root___eval (vlSelf=0x7ffff399b080) at Vsim___024root__DepSet_h104c642d__0.cpp:57 #2 0x00005555555ff36c in Vsim::eval_step (this=0x555555669300) at Vsim.cpp:95 #3 0x00005555555b96ba in Vsim::eval (this=<optimized out>) at ./Vsim.h:64 #4 litex_sim_eval (vsim=<optimized out>, time_ps=724193000000) at /home/msyksphinz/work/litex/litex_repo/litex/litex/build/sim/core/veril.cpp:28 #5 0x0000555555600434 in cb (sock=<optimized out>, which=<optimized out>, arg=0x555555669300) at /home/msyksphinz/work/litex/litex_repo/litex/litex/build/sim/core/sim.c:189 #6 0x00007ffff7d4013f in ?? () from /lib/x86_64-linux-gnu/libevent-2.1.so.7 #7 0x00007ffff7d4087f in event_base_loop () from /lib/x86_64-linux-gnu/libevent-2.1.so.7 #8 0x00005555555b9524 in main (argc=<optimized out>, argv=<optimized out>) at /home/msyksphinz/work/litex/litex_repo/litex/litex/build/sim/core/sim.c:248
なるほど。自分のSoC環境ではどうか?
(gdb) run Starting program: /home/kimura/work/riscv/litex/litex_scariv/litex/build/sim/gateware/obj_dir/Vsim [Thread debugging using libthread_db enabled] Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1". [serial2console] loaded (0x5555572d0ef0) [gmii_ethernet] loaded (0x5555572d0ef0) [ethernet] loaded (0x5555572d0ef0) [clocker] loaded [xgmii_ethernet] loaded (0x5555572d0ef0) [serial2tcp] loaded (0x5555572d0ef0) [spdeeprom] loaded (addr = 0x0) [clocker] sys_clk: freq_hz=1000000, phase_deg=0 Program received signal SIGINT, Interrupt. Vsim___024root___combo__TOP__256 (vlSelf=0x7ffff786b080) at Vsim___024root__DepSet_h104c642d__306.cpp:3700 ^Cbt 3700 >> 5U)] (gdb) Quit (gdb) bt #0 Vsim___024root___combo__TOP__256 (vlSelf=0x7ffff786b080) at Vsim___024root__DepSet_h104c642d__306.cpp:3700 #1 0x00005555565671c6 in Vsim___024root___eval (vlSelf=0x7ffff786b080) at Vsim___024root__DepSet_hb1836b75__313.cpp:1263 #2 0x0000555556565e8a in Vsim::eval_step (this=0x5555572d2300) at Vsim.cpp:267 #3 0x0000555556554e65 in Vsim::eval (this=0x7ffff786b080, this@entry=0x5555572d2300) at ./Vsim.h:276 #4 litex_sim_eval (vsim=0x7ffff786b080, vsim@entry=0x5555572d2300, time_ps=0) at /home/kimura/work/riscv/litex/litex_scariv/litex/litex/build/sim/core/veril.cpp:28 #5 0x0000555557139ae3 in cb (sock=<optimized out>, which=<optimized out>, arg=0x5555572d2300) at /home/kimura/work/riscv/litex/litex_scariv/litex/litex/build/sim/core/sim.c:189 #6 0x00007ffff7c32f58 in ?? () from /lib/x86_64-linux-gnu/libevent-2.1.so.7 #7 0x00007ffff7c348a7 in event_base_loop () from /lib/x86_64-linux-gnu/libevent-2.1.so.7 #8 0x0000555556554cf0 in main (argc=<optimized out>, argv=<optimized out>) at /home/kimura/work/riscv/litex/litex_scariv/litex/litex/build/sim/core/sim.c:248
ふむ、Vsim.cpp
のeval()
ステップを慎重に観察する必要がありそうだ。