FPGAというより、コンピュータアーキテクチャかもね! カテゴリ別記事インデックス https://msyksphinz.github.io/github_pages/

FreeRTOSをRISC-V Spike ISSで動作させるためのオプション


$ spike --help
spike: unrecognized option --help
usage: spike [host options] <target program> [target options]
Host Options:
  -p<n>                 Simulate <n> processors [default 1]
  -m<n>                 Provide <n> MiB of target memory [default 4096]
  -d                    Interactive debug mode
  -g                    Track histogram of PCs
  -l                    Generate a log of execution
  -h                    Print this help message
  -H                 Start halted, allowing a debugger to connect
  --isa=<name>          RISC-V ISA string [default RV32IMA]
  --ic=<S>:<W>:<B>      Instantiate a cache model with S sets,
  --dc=<S>:<W>:<B>        W ways, and B-byte blocks (with S and
  --l2=<S>:<W>:<B>        B both powers of 2).
  --extension=<name>    Specify RoCC Extension
  --extlib=<name>       Shared library to load
  --gdb-port=<port>  Listen on <port> for gdb to connect
  --dump-config-string  Print platform configuration string and exit


$ spike -l riscv-spike.elf > riscv-spike.sw.log 2>&1


warning: only got 2934964224 bytes of target mem (wanted 4026531840)
core   0: 0x0000000000001000 (0x7ffff297) auipc   t0, 0x7ffff
core   0: 0x0000000000001004 (0x00028067) jr      t0
core   0: 0xffffffff80000000 (0x00002fb7) lui     t6, 0x2
core   0: 0xffffffff80000004 (0x800f8f9b) addiw   t6, t6, -2048
core   0: exception trap_illegal_instruction, epc 0xffffffff80000004
core   0: 0x0000000000001010 (0x00000000) addi    s0, sp, 0
core   0: exception trap_illegal_instruction, epc 0x0000000000001010


  --isa=<name>          RISC-V ISA string [default RV32IMA]


$ spike --isa=RV64IMA riscv-spike.elf
warning: only got 2934964224 bytes of target mem (wanted 4026531840)


-    spike $(PROG).elf
+    spike --isa=RV64IMA $(PROG).elf