Vivado Simulatorを使ってUVMに入門する (4. master と slave に分けてシミュレーション)

以下のサイトを読みながらUVMについて勉強をしている。

sites.google.com

次はUVMの環境をマスターとスレーブに分けて環境を構築する。これまで作ったsequencer / driver / monitor をそれぞれmasterとslaveに分けた。

• sample_master_agent.sv

class sample_master_agent extends uvm_agent;
  `uvm_component_utils(sample_master_agent)
  sample_master_driver    driver;
  sample_master_monitor   monitor;
  sample_master_sequencer sequencer;
  function new (string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    driver    = sample_master_driver::type_id::create("driver", this);
    monitor   = sample_master_monitor::type_id::create("monitor", this);
    sequencer = sample_master_sequencer::type_id::create("sequencer", this);
  endfunction

  function void connect_phase (uvm_phase phase);
    if (get_is_active() == UVM_ACTIVE) begin
      driver.seq_item_port.connect(sequencer.seq_item_export);
    end
  endfunction // connect_phase

  task run_phase(uvm_phase phase);
    uvm_report_info("AGENT", "Hi");
  endtask // run_phase

endclass

• sample_slave_agent.sv

class sample_slave_agent extends uvm_agent;
  `uvm_component_utils(sample_slave_agent)
  sample_slave_driver    driver;
  // sample_slave_monitor   monitor;
  sample_slave_sequencer sequencer;
  function new (string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    driver    = sample_slave_driver::type_id::create("driver", this);
    // monitor   = sample_slave_monitor::type_id::create("monitor", this);
    sequencer = sample_slave_sequencer::type_id::create("sequencer", this);
  endfunction

  function void connect_phase (uvm_phase phase);
    if (get_is_active() == UVM_ACTIVE) begin
      driver.seq_item_port.connect(sequencer.seq_item_export);
    end
  endfunction // connect_phase

  task run_phase(uvm_phase phase);
    uvm_report_info("AGENT", "Hi");
  endtask // run_phase

endclass

解説の通りに実装してVivado Simulatorでコンパイルしてみたのだが、どうも上手く行っていない気がする？masterからのリクエストが出ていないのか、ちゃんとメッセージが返ってきていないような気がする。

UVM_INFO @ 0: uvm_test_top.env [ENV] Hello ENV
UVM_INFO @ 0: uvm_test_top.env.slave [AGENT] Hi
UVM_INFO @ 0: uvm_test_top.env.slave.sequencer [SEQR] Hi
UVM_INFO @ 0: uvm_test_top.env.slave.driver [DRIVER] Hi
UVM_INFO @ 0: uvm_test_top.env.master [AGENT] Hi
UVM_INFO @ 0: uvm_test_top.env.master.sequencer [SEQR] Hi
UVM_INFO @ 0: uvm_test_top.env.master.monitor [MONITOR] Hi
UVM_INFO @ 0: uvm_test_top.env.master.driver [DRIVER] Hi
Hello SEQ
UVM_INFO @ 0: uvm_test_top.env.master.sequencer@@write_seq [SEQ] read data is 00f
UVM_INFO /proj/xbuilds/SWIP/2020.2_0711_1805/installs/lin64/Vivado/2020.2/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(13673) @ 0: reporter [UVM/REPORT/SERVER] [UVMTOP]     1

うーん、もうちょっと解析したい。