GCC5.1 で MIPS Release6がサポートされている！早速使ってみなければ！
- MIPS Releases 3 and 5 are now directly supported. Use the command-line options -mips32r3, -mips64r3, -mips32r5 and -mips64r5 to enable code-generation for these processors.
- The Imagination P5600 processor is now supported using the -march=p5600 command-line option.
- The Cavium Octeon3 processor is now supported using the -march=octeon3 command-line option.
- MIPS Release 6 is now supported using the -mips32r6 and -mips64r6 command-line options.
- The o32 ABI has been modified and extended. The o32 64-bit floating-point register support is now obsolete and has been removed. It has been replaced by three ABI extensions FPXX, FP64A, and FP64. The meaning of the -mfp64 command-line option has changed. It is now used to enable the FP64A and FP64 ABI extensions.
- The FPXX extension requires that code generated to access double-precision values use even-numbered registers. Code that adheres to this extension is link-compatible with all other o32 double-precision ABI variants and will execute correctly in all hardware FPU modes. The command-line options -mabi=32 -mfpxx can be used to enable this extension. MIPS II is the minimum processor required.
- The o32 FP64A extension requires that floating-point registers be 64-bit and odd-numbered single-precision registers are not allowed. Code that adheres to the o32 FP64A variant is link-compatible with all other o32 double-precision ABI variants. The command-line options -mabi=32 -mfp64 -mno-odd-spreg can be used to enable this extension. MIPS32R2 is the minimum processor required.
- The o32 FP64 extension also requires that floating-point registers be 64-bit, but permits the use of single-precision registers. Code that adheres to the o32 FP64 variant is link-compatible with o32 FPXX and o32 FP64A variants only, i.e. it is not compatible with the original o32 double-precision ABI. The command-line options -mabi=32 -mfp64 -modd-spreg can be used to enable this extension. MIPS32R2 is the minimum processor required.
- The new ABI variants can be enabled by default using the configure time options --with-fp-32=[32|xx|64] and --with(out)-odd-sp-reg-32. It is strongly recommended that all vendors begin to set o32 FPXX as the default ABI. This will be required to run the generated code on MIPSR5 cores in conjunction with future MIPS SIMD (MSA) code and MIPSR6 cores.
- GCC will now pass all floating-point options to the assembler if GNU binutils 2.25 is used. As a result, any inline assembly code that uses hard-float instructions should be amended to include a .set directive to override the global assembler options when compiling for soft-float targets.