オープンソース・アウトオブオーダCPU NaxRiscvを概観する (2.)

msyksphinz.hatenablog.com

NaxRiscvのVerilogコードだが、やっぱり何が書いてあるのかさっぱりわからない。

大まかなシステム階層は以下のようになっているのだが、これだけだと分からないよね。

module NaxRiscv (
  TranslatorWithRollback integer_RfTranslationPlugin_logic_impl ();
  AllocatorMultiPortMem integer_RfAllocationPlugin_logic_allocator ();
  DataCache DataCachePlugin_logic_cache ();
  StreamFifoLowLatency CommitPlugin_logic_free_lineEventStream_fifo ();
  DivRadix4 EU0_DivPlugin_logic_div ();
  PrefetchPredictor Lsu2Plugin_logic_prefetch_predictor ();
  IssueQueue DispatchPlugin_logic_queue ();
  RegFileAsync integer_RegFilePlugin_logic_regfile_fpga ();
  DependencyStorage RfDependencyPlugin_logic_forRf_integer_impl ();
  RamAsyncMwMux BranchContextPlugin_logic_mem_earlyBranch ();
  RamAsyncMwMux_1 BranchContextPlugin_logic_mem_finalBranch ();
  RamAsyncMwXor Lsu2Plugin_logic_lq_mem_sqAlloc ();
  RamAsyncMwXor_1 Lsu2Plugin_logic_lq_mem_doSpecial ();
  RamAsyncMwXor_9 Lsu2Plugin_logic_lq_mem_needTranslation ();
  RamAsyncMwXor_10 Lsu2Plugin_logic_sq_mem_needTranslation ();
  RamAsyncMwXor_1 Lsu2Plugin_logic_sq_mem_feededOnce ();
  RamAsyncMwXor_1 Lsu2Plugin_logic_sq_mem_doSpecial ();
  RamAsyncMwXor_6 Lsu2Plugin_logic_sq_mem_lqAlloc ();
  RamAsyncMwMux_2 BranchContextPlugin_free_dispatchMem_mem ();
  RamAsyncMwXor_7 RobPlugin_logic_storage_BRANCH_TAKEN_banks_0 ();

後半のRAMの部分は何がFPGAのRAMを使っているかくらいは想像できる。

一応、インタフェースの接続関係から動作を観察するしかない、ということかもしれない。

module NaxRiscv (
  output wire          FetchCachePlugin_mem_cmd_valid,
  input  wire          FetchCachePlugin_mem_cmd_ready,
  output wire [31:0]   FetchCachePlugin_mem_cmd_payload_address,
  output wire          FetchCachePlugin_mem_cmd_payload_io,
  input  wire          FetchCachePlugin_mem_rsp_valid,
  output wire          FetchCachePlugin_mem_rsp_ready,
  input  wire [63:0]   FetchCachePlugin_mem_rsp_payload_data,
  input  wire          FetchCachePlugin_mem_rsp_payload_error,
  input  wire          PrivilegedPlugin_io_int_machine_timer /* verilator public */ ,
  input  wire          PrivilegedPlugin_io_int_machine_software /* verilator public */ ,
  input  wire          PrivilegedPlugin_io_int_machine_external /* verilator public */ ,
  input  wire          PrivilegedPlugin_io_int_supervisor_external /* verilator public */ ,
  input  wire [63:0]   PrivilegedPlugin_io_rdtime,
  output wire          LsuPlugin_peripheralBus_cmd_valid /* verilator public */ ,
  input  wire          LsuPlugin_peripheralBus_cmd_ready /* verilator public */ ,
  output wire          LsuPlugin_peripheralBus_cmd_payload_write /* verilator public */ ,
  output wire [31:0]   LsuPlugin_peripheralBus_cmd_payload_address /* verilator public */ ,
  output wire [31:0]   LsuPlugin_peripheralBus_cmd_payload_data /* verilator public */ ,
  output wire [3:0]    LsuPlugin_peripheralBus_cmd_payload_mask /* verilator public */ ,
  output wire [1:0]    LsuPlugin_peripheralBus_cmd_payload_size /* verilator public */ ,
  input  wire          LsuPlugin_peripheralBus_rsp_valid /* verilator public */ ,
  input  wire          LsuPlugin_peripheralBus_rsp_payload_error /* verilator public */ ,
  input  wire [31:0]   LsuPlugin_peripheralBus_rsp_payload_data /* verilator public */ ,
  output wire          DataCachePlugin_mem_read_cmd_valid,
  input  wire          DataCachePlugin_mem_read_cmd_ready,
  output wire [0:0]    DataCachePlugin_mem_read_cmd_payload_id,
  output wire [31:0]   DataCachePlugin_mem_read_cmd_payload_address,
  input  wire          DataCachePlugin_mem_read_rsp_valid,
  output wire          DataCachePlugin_mem_read_rsp_ready,
  input  wire [0:0]    DataCachePlugin_mem_read_rsp_payload_id,
  input  wire [63:0]   DataCachePlugin_mem_read_rsp_payload_data,
  input  wire          DataCachePlugin_mem_read_rsp_payload_error,
  output wire          DataCachePlugin_mem_write_cmd_valid,
  input  wire          DataCachePlugin_mem_write_cmd_ready,
  output wire          DataCachePlugin_mem_write_cmd_payload_last,
  output wire [31:0]   DataCachePlugin_mem_write_cmd_payload_fragment_address,
  output wire [63:0]   DataCachePlugin_mem_write_cmd_payload_fragment_data,
  output wire [0:0]    DataCachePlugin_mem_write_cmd_payload_fragment_id,
  input  wire          DataCachePlugin_mem_write_rsp_valid,
  input  wire          DataCachePlugin_mem_write_rsp_payload_error,
  input  wire [0:0]    DataCachePlugin_mem_write_rsp_payload_id,
  input  wire          clk,
  input  wire          reset
);

なんか例えば命令キャッシュが命令をフェッチするようなところは、この辺だと思う。 でもなんだか良く分からんな..

    val refill = new Area {
      val start = new Area{
        val valid = False
        val address = UInt(PHYSICAL_WIDTH bits)
        val wayToAllocate = UInt(log2Up(wayCount) bits)
        val isIo = Bool()
      }
    
      val fire = False
      val valid = RegInit(False) clearWhen (fire)
      val address = KeepAttribute(Reg(UInt(PHYSICAL_WIDTH bits)))
      val isIo = Reg(Bool())
      val hadError = RegInit(False)
      val wayToAllocate = Reg(UInt(log2Up(wayCount) bits))

      import spinal.core.sim._
      val pushCounter = Reg(UInt(32 bits)) init (0) simPublic()

      when(!valid){
        when(start.valid){
          valid := True
          pushCounter := pushCounter + 1
        }
        address := start.address
        isIo := start.isIo
        wayToAllocate := start.wayToAllocate
      }