結構時間が空いてしまった。とりあえずYosysの環境を構築して、Chipyardで構築した簡単なVerilog機構はコンパイルできるようにしてみよう。

インストール

git clone https://github.com/YosysHQ/yosys.git
git co yosys-0.19
make -j$(nproc)
make install PREFIX=${PWD}/../usr

実行手順

Yosysを実行するためのスクリプトは以下になる。

synth.cmd

read -sv chipyard.TestHarness.RocketConfig.top.v
hierarchy -top RocketTile
proc; opt
write_verilog chipyard.TestHarness.RocketConfig.synth.v
# write_cxxrtl  chipyard.TestHarness.RocketConfig.synth.cpp
write_rtlil   chipyard.TestHarness.RocketConfig.synth.rtlil
write_json    chipyard.TestHarness.RocketConfig.synth.json

スクリプトを実行する。論理合成するわけではなく、Elaborationする程度であれば数秒で終了する。

../usr/bin/yosys -s synth.cmd

RocketTileモジュールは以下のようになる。

module RocketTile(clock, reset, auto_wfi_out_0, auto_int_local_in_3_0, auto_int_local_in_2_0, auto_int_local_in_1_0, auto_int_local_in_1_1, auto_int_local_in_0_0, auto_hartid_in, auto_tl_other_masters_out_a_ready, auto_tl_other_masters_out_a_valid, auto_tl_other_masters_out_a_bits_opcode, auto_tl_other_masters_out_a_bits_param, auto_tl_other_masters_out_a_bits_size, auto_tl_other_masters_out_a_bits_source, auto_tl_other_masters_out_a_bits_address, auto_tl_other_masters_out_a_bits_mask, auto_tl_other_masters_out_a_bits_data, auto_tl_other_masters_out_b_ready, auto_tl_other_masters_out_b_valid, auto_tl_other_masters_out_b_bits_opcode
, auto_tl_other_masters_out_b_bits_param, auto_tl_other_masters_out_b_bits_size, auto_tl_other_masters_out_b_bits_source, auto_tl_other_masters_out_b_bits_address, auto_tl_other_masters_out_b_bits_mask, auto_tl_other_masters_out_b_bits_corrupt, auto_tl_other_masters_out_c_ready, auto_tl_other_masters_out_c_valid, auto_tl_other_masters_out_c_bits_opcode, auto_tl_other_masters_out_c_bits_param, auto_tl_other_masters_out_c_bits_size, auto_tl_other_masters_out_c_bits_source, auto_tl_other_masters_out_c_bits_address, auto_tl_other_masters_out_c_bits_data, auto_tl_other_masters_out_d_ready, auto_tl_other_masters_out_d_valid, auto_tl_other_masters_out_d_bits_opcode, auto_tl_other_masters_out_d_bits_param, auto_tl_other_masters_out_d_bits_size, auto_tl_other_masters_out_d_bits_source, auto_tl_other_masters_out_d_bits_sink
, auto_tl_other_masters_out_d_bits_denied, auto_tl_other_masters_out_d_bits_data, auto_tl_other_masters_out_d_bits_corrupt, auto_tl_other_masters_out_e_ready, auto_tl_other_masters_out_e_valid, auto_tl_other_masters_out_e_bits_sink);
  (* src = "chipyard.TestHarness.RocketConfig.top.v:212527.17-212527.31" *)
  input auto_hartid_in;
  wire auto_hartid_in;
  (* src = "chipyard.TestHarness.RocketConfig.top.v:212526.17-212526.38" *)
  input auto_int_local_in_0_0;
  wire auto_int_local_in_0_0;
  (* src = "chipyard.TestHarness.RocketConfig.top.v:212524.17-212524.38" *)
  input auto_int_local_in_1_0;
  wire auto_int_local_in_1_0;
  (* src = "chipyard.TestHarness.RocketConfig.top.v:212525.17-212525.38" *)
  input auto_int_local_in_1_1;
  wire auto_int_local_in_1_1;
  (* src = "chipyard.TestHarness.RocketConfig.top.v:212523.17-212523.38" *)
  input auto_int_local_in_2_0;
  wire auto_int_local_in_2_0;
  (* src = "chipyard.TestHarness.RocketConfig.top.v:212522.17-212522.38" *)
...

JSONファイルも生成できるようだ。

    "RocketTile": {
      "attributes": {
        "hdlname": "\\RocketTile",
        "top": "00000000000000000000000000000001",
        "src": "chipyard.TestHarness.RocketConfig.top.v:212518.1-214822.10"
      },
      "ports": {
        "clock": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "reset": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "auto_wfi_out_0": {
          "direction": "output",
          "bits": [ 4 ]
        },