Chisel → FIRRTL → Verilog で必要なこと

とりあえず試行錯誤しながら、必要なファイル群は以下のような構成になっている。

必要なのはsbtを起動させるためのplugins.sbtとbuild.sbtだ。

project/plugins.sbt

resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"
addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2")
addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1")
addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3")
addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1")
addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")

build.sbt

import sbt.complete._
import sbt.complete.DefaultParsers._
import xerial.sbt.pack._
import sys.process._

enablePlugins(PackPlugin)

lazy val commonSettings = Seq(
  organization := "berkeley",
  version      := "1.2",
  scalaVersion := "2.11.12",
  parallelExecution in Global := false,
  traceLevel   := 15,
  scalacOptions ++= Seq("-deprecation","-unchecked"),
  libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value),
  addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)
)

lazy val chisel = (project in file("chisel3")).settings(commonSettings)
lazy val hardfloat  = project.dependsOn(chisel).settings(commonSettings)
lazy val macros = (project in file("macros")).settings(commonSettings)
lazy val rocketchip = (project in file("."))
  .settings(commonSettings, chipSettings)
  .dependsOn(chisel, hardfloat, macros)

lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
lazy val make = inputKey[Unit]("trigger backend-specific makefile command")
val setMake = NotSpace ~ ( Space ~> NotSpace )

val chipSettings = Seq(
  addons := {
    val a = sys.env.getOrElse("ROCKETCHIP_ADDONS", "")
    println(s"Using addons: $a")
    a.split(" ")
  },
  unmanagedSourceDirectories in Compile ++= addons.value.map(baseDirectory.value / _ / "src/main/scala"),
  mainClass in (Compile, run) := Some("rocketchip.Generator"),
  make := {
    val jobs = java.lang.Runtime.getRuntime.availableProcessors
    val (makeDir, target) = setMake.parsed
    (run in Compile).evaluated
    s"make -C $makeDir  -j $jobs $target".!
  }
)

全体ファイル構成は以下のようになっている。

.
├── Makefrag
├── Verilator.mk
├── build.sbt
├── chisel3
│   ├── Makefile
│   ├── README.md
│   ├── bin
│   ├── build.sbt
│   ├── chiselFrontend
│   ├── coreMacros
│   ├── doc
│   ├── project
│   ├── root-doc.txt
│   ├── scalastyle-config.xml
│   ├── scalastyle-test-config.xml
│   └── src
├── emulator
│   ├── Makefile
│   └── Makefrag-verilator
├── firrtl
│   ├── Makefile
│   ├── README.md
│   ├── TODO
│   ├── _config.yml
│   ├── build.sbt
│   ├── notes
│   ├── project
│   ├── regress
│   ├── root-doc.txt
│   ├── scalastyle-config.xml
│   ├── scalastyle-test-config.xml
│   ├── scripts
│   ├── spec
│   ├── src
│   ├── test
│   └── utils
├── project
│   ├── build.properties
│   └── plugins.sbt
├── sbt-launch.jar
├── src
│   └── main
└── vsim
    ├── Makefile
    ├── Makefrag
    └── Makefrag-verilog

ちなみに、Scalaの本を買った。紙媒体がなぜか売り切れ状態だったので達人出版会で購入。

Chiselの実装が意味が分からない部分があるので、解き明かしていかなければ。