前回の続き、今回は、OpenOCDを使って、コンパイルしたバイナリファイルをHiFive1に書き込み、実行する。

OpenOCDを使った書き込みシーケンスを探す

Arduinoのディレクトリを探して、OpenOCDを使ったバイナリファイルへのアップロードをしているスクリプトを見つけた。

packages/sifive/hardware/riscv/1.0.2/freedom-e-sdk/bsp/tools/openocd_upload.sh

あーこれだな。これにバイナリファイルと、構成ファイルを指定すればHiFive1への書き込みができるに違いない。

export PATH=/home/masayuki/.arduino15/packages/sifive/tools/openocd/9bab0782d313679bb0bfb634e6e87c757b8d5503/bin/:${PATH}
./packages/sifive/hardware/riscv/1.0.2/freedom-e-sdk/bsp/tools/openocd_upload.sh /home/masayuki/work/hifive1/uart_test/uart_test ./packages/sifive/hardware/riscv/1.0.2/freedom-e-sdk/bsp/env/freedom-e300-hifive1/openocd.cfg

openocd.cfgファイルは、ボードの情報、JTAGの書き込み速度などの情報を持っているスクリプトだ。

adapter_khz     10000

interface ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010
...
flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
#reset -- This type of reset is not implemented yet
if {[ info exists pulse_srst]} {
  ftdi_set_signal nSRST 0
  ftdi_set_signal nSRST z
  #Wait for the reset stretcher
  #It will work without this, but
  #will incur lots of delays for later commands.
  sleep 1500
}
halt
#flash protect 0 64 last off

という訳で実行してみた。無事に書き込みが行われ、プログラムが実行されたようだ。

$ ./packages/sifive/hardware/riscv/1.0.2/freedom-e-sdk/bsp/tools/openocd_upload.sh /home/masayuki/work/hifive1/uart_test/uart_test ./packages/sifive/hardware/riscv/1.0.2/freedom-e-sdk/bsp/env/freedom-
e300-hifive1/openocd.cfg
+ openocd -f ./packages/sifive/hardware/riscv/1.0.2/freedom-e-sdk/bsp/env/freedom-e300-hifive1/openocd.cfg -c 'flash protect 0 64 last off; program /home/masayuki/work/hifive1/uart_test/uart_test verify; resume 0x20400000; exit'
+ tee openocd_upload.log
Open On-Chip Debugger 0.10.0-dev-g9bab078 (2017-02-02-01:39)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x10e31913 (mfg: 0x489 (<unknown>), part: 0x0e31, ver: 0x1)
Info : dtmcontrol_idle=5, dbus_busy_delay=1, interrupt_high_delay=0
Info : dtmcontrol_idle=5, dbus_busy_delay=1, interrupt_high_delay=1
Info : Examined RISCV core; XLEN=32, misa=0x40001105
Info : dtmcontrol_idle=5, dbus_busy_delay=1, interrupt_high_delay=2
Info : dtmcontrol_idle=5, dbus_busy_delay=1, interrupt_high_delay=3
Info : dtmcontrol_idle=5, dbus_busy_delay=1, interrupt_high_delay=4
Info : dtmcontrol_idle=5, dbus_busy_delay=1, interrupt_high_delay=5
...
Info : dtmcontrol_idle=5, dbus_busy_delay=2, interrupt_high_delay=249
Info : Retrying memory read starting from 0x20400000 with more delays
Info : dtmcontrol_idle=5, dbus_busy_delay=2, interrupt_high_delay=274
Info : Retrying memory read starting from 0x20400000 with more delays
Info : dtmcontrol_idle=5, dbus_busy_delay=2, interrupt_high_delay=302
Info : Retrying memory read starting from 0x20400000 with more delays
Info : dtmcontrol_idle=5, dbus_busy_delay=2, interrupt_high_delay=333
Info : Retrying memory read starting from 0x20400000 with more delays
verified 4492 bytes in 0.361002s (12.152 KiB/s)
** Verified OK **
halted at 0x20400004 due to step